Abstract: Provided are apparatus, methods and techniques to perform a readout of a plurality (N) of Time Delay and Integration (TDI) pixel registers to receive respective signal charges at a plurality (N) of sense nodes (SNs). The readout uses a plurality (N) of charge steering (CST) gates to steer and demultiplex respective charges from respective pixel registers to corresponding SNs. Output is provided from the SNs for producing respective digital values (e.g. through parallel conversion using ADCs). In an embodiment, charges are transferred vertically to the CSTs for demultiplexing horizontally to the SNs. The CSTs may be configured in a multi-stage configuration to assist with good charge transfer. The CSTs may be associated with a barrier implant to assist with proper charge steering.

Abstract: A plural line CMOS sensor array device is provided with sensor cells arranged in a matrix of coordinate-wise rows and columns. Each cell comprises a photosensitive area, an output node, and a transfer gate for selectively interconnecting the photosensitive area and the output node. Along at least a first coordinate direction adjacent cells are functionally configured as mutually mirror-symmetric structures in that their proximate output nodes are facing each other and are arranged for separately feeding a respective output channel. Preferably, also in a second coordinate direction adjacent cells are functionally configured as mutually mirror-symmetric structures in that their proximate output nodes are facing each other and all such facing output nodes are separately feeding a respective column-directed output channel.

Abstract: A plural line CMOS sensor array device is provided with sensor cells arranged in a matrix of coordinate-wise rows and columns Each cell comprises a photosensitive area, an output node, and a transfer gate for selectively interconnecting the photo-sensitive area and the output node. Along at least a first coordinate direction adjacent cells are functionally configured as mutually mirror-symmetric structures in that their proximate output nodes are facing each other and are arranged for separately feeding a respective output channel. Preferably, also in a second coordinate direction adjacent cells are functionally configured as mutually mirror-symmetric structures in that their proximate output nodes are facing each other and all such facing output nodes are separately feeding a respective column-directed output channel.

Abstract: A method of using a line-scan sensor device to scan an image includes determining and removing. The device includes sensor cells arranged in a matrix of rows and columns. The determining includes determining when a pixel signal value from a pixel in a first row and in a column deviates from a pixel signal value from a pixel in a second row and in said column. The removing includes removing the pixel signal value of the pixel in the first row and in said column when the pixel signal value from the pixel in the first row and in said column deviates from the pixel signal value from the pixel in the second row and in said column. The pixel in the first row and in said column images a portion of the image and the pixel in the second row and in said column images the same portion of the image.

Abstract: A plural line CMOS sensor array device is provided with sensor cells arranged in a matrix of coordinate-wise rows and columns. Each cell comprises a photosensitive area, an output node, and a transfer gate for selectively interconnecting the photosensitive area and the output node. Along at least a first coordinate direction adjacent cells are functionally configured as mutually mirror-symmetric structures in that their proximate output nodes are facing each other and are arranged for separately feeding a respective output channel. Preferably, also in a second coordinate direction adjacent cells are functionally configured as mutually mirror-symmetric structures in that their proximate output nodes are facing each other and all such facing output nodes are separately feeding a respective column-directed output channel.

Abstract: A plural line CMOS sensor array device is provided with sensor cells arranged in a matrix of coordinate-wise rows and columns. Each cell comprises a photosensitive area, an output node, and a transfer gate for selectively interconnecting the photosensitive area and the output node. Along at least a first coordinate direction adjacent cells are functionally configured as mutually mirror-symmetric structures in that their proximate output nodes are facing each other and are arranged for separately feeding a respective output channel. Preferably, also in a second coordinate direction adjacent cells are functionally configured as mutually mirror-symmetric structures in that their proximate output nodes are facing each other and all such facing output nodes are separately feeding a respective column-directed output channel.

Abstract: A method includes a first step followed by a second step. The first step includes transferring photo charges in a delay register into a first readout register, transferring photo charges in a first storage register into the delay register, and transferring photo charges in a second storage register into a second readout register. The second step includes collecting photo charges in the first storage register, collecting photo charges in the second storage register, shifting photo charges in the first readout register toward a first output, and shifting photo charges in the second readout register toward a second output.

Abstract: A line scan sensor includes first and second rows of pixels, corresponding first and second readout registers, and a first clocking structure disposed between the first row of pixels and the first readout register. The first clocking structure includes a transfer gate electrode and a delay well electrode. In an alternative embodiment, a method includes a first step followed by a second step. The first step includes transferring photo charges in a delay register into a first readout register, transferring photo charges in a first storage register into the delay register, and transferring photo charges in a second storage register into the second readout register. The second step includes collecting photo charges in the first storage register, collecting photo charges in the second register, shifting photo charges in a first readout register toward a first out put, and shifting photo charges in a second readout register toward a second output.

Abstract: A TDI sensor includes a column of pixels ordered from an initial pixel to a final pixel where each pixel includes reticulated clock conductors arranged to define a reticulation area and a pixel charge handling capacity. The reticulation area of a pixel increases from the final pixel to the initial pixel, and the pixel charge handling capacity increases from the initial pixel to the final pixel. The sensor includes a first bus structure of polysilicon, where the bus structure includes register element sets and each register element set includes a plurality of clock conductors. Each register element set includes a corresponding pixel reticulation area, and the pixel reticulation area of a first register element set is unequal to a pixel reticulation area of another register element set. The sensor also includes a second bus structure of metal disposed substantially diagonally to the first bus structure. The second bus structure includes clock bus sets, and each clock bus set includes bus conductors.

Abstract: A method of using a pinned photodiode pixel for high-speed motion-capture CMOS image sensors uses a pinned photodiode in a five-transistor pixel so that the channel region of the photodiode is completely voided of charge after reset and readout operations. An exemplary method includes applying an exposure control clock signal to a gate electrode of an exposure control transistor of a five-transistor pixel, applying a pixel preset voltage to a drain of the exposure control transistor, and switching the exposure control clock signal. The exposure control transistor is coupled between a pinned photodiode of the pixel and the pixel preset voltage. The switching the exposure control clock signal turns off the exposure control transistor at a beginning of an integration cycle after substantially all signal charge has drained out of the pinned photodiode and across the exposure control transistor so that the pinned photodiode is fully voided of majority carriers.

Abstract: A pixel includes five transistors, a pinned photodiode and a storage node. A first transistor is coupled between the pinned photodiode and the storage node. A second transistor is coupled between the storage node and an output drain voltage. A third transistor is coupled between the pinned photodiode and a pixel reset voltage. The pixel reset voltage is different than the output drain voltage.

Abstract: a pixel is formed in a substrate having a first conductivity type, the pixel being coupled to a register for output. The pixel includes a pixel channel of a second conductivity type formed in the substrate, a transfer gate electrode, a storage gate electrode and a photodiode. The pixel channel includes a transfer portion at a first end of the pixel channel proximal to the register, a diode portion at a second end distal to the register and a storage portion between the transfer portion and the diode portion. The transfer gate electrode is insulatively spaced over the transfer portion, and the storage gate electrode is insulatively spaced over the storage portion. The diode is formed within the diode portion using the storage gate electrode as a mask.

Abstract: A CCD sensor includes a readout register formed in substrate, the readout register including a channel, a bus structure and a connection structure. The bus structure includes plural spaced element sets, each element set including a first clock conductor. The first clock conductor of a first element set is a dual function conductor. The connection structure isolates the dual function conductor while coupling together the first clock conductor of each other set of the element sets. Alternatively, the sensor includes vertical and readout registers formed in a well in a substrate. The vertical register includes a vertical channel, a vertical bus structure and a vertical connection structure, and the readout register includes a readout channel, a readout bus structure and a readout connection structure. The readout bus structure includes plural spaced readout element sets, each readout element set including a first readout clock conductor.