Abstract: A memory device includes a row-hammer tracking circuit configured to: generate short interval signals each having one of first to n-th lengths based on input intervals between active commands, and generate a rate control signal based on whether a pattern of the short interval signals corresponds to a row-hammer attack pattern; and a target command issue circuit configured to adjust a frequency of a target refresh operation according to the rate control signal.

Abstract: An integrated circuit includes a sampling control circuit configured to generate a sampling enable signal by dividing a sampling period into a plurality of sub-sections according to an active counting signal generated by counting a number of inputs of an active signal during the sampling period, and comparing the active counting signal with a random signal for each sub-section; and a sampling circuit configured to sample and store an input address according to the sampling enable signal.

Abstract: An integrated circuit includes a sampling control circuit configured to generate a sampling enable signal by dividing a sampling period into a plurality of sub-sections according to an active counting signal generated by counting a number of inputs of an active signal during the sampling period, and comparing the active counting signal with a random signal for each sub-section; and a sampling circuit configured to sample and store an input address according to the sampling enable signal.

Abstract: A semiconductor device includes a peripheral circuit and a core circuit. The peripheral circuit enters a smart refresh mode in which a smart refresh operation is performed based on a command. The peripheral circuit generates a latch address signal from a target address signal to output the latch address signal through a global input/output (I/O) line in the smart refresh mode. The core circuit performs an adding operation and a subtracting operation of the latch address signal to generate first and second internal address signals. The core circuit performs the smart refresh operation for first and second banks based on the first and second internal address signals.

Abstract: A semiconductor device includes a peripheral circuit and a core circuit. The peripheral circuit enters a smart refresh mode in which a smart refresh operation is performed based on a command. The peripheral circuit generates a latch address signal from a target address signal to output the latch address signal through a global input/output (I/O) line in the smart refresh mode. The core circuit performs an adding operation and a subtracting operation of the latch address signal to generate first and second internal address signals. The core circuit performs the smart refresh operation for first and second banks based on the first and second internal address signals.

Abstract: A semiconductor memory device includes a first count circuit suitable for counting a first clock signal which continuously toggles in each burst refresh cycle, and generating a first count code signal, based on a burst refresh command signal; a cycle guide circuit suitable for generating a second clock signal which toggles once in each burst refresh cycle, based on the burst refresh command signal and a precharge signal; a second count circuit suitable for counting the second clock signal and generating a second count code signal; and a control circuit suitable for generating a latch control signal for latching a target address in each burst refresh cycle, based on the first count code signal and the second count code signal.

Abstract: A semiconductor memory device includes a first count circuit suitable for counting a first clock signal which continuously toggles in each burst refresh cycle, and generating a first count code signal, based on a burst refresh command signal; a cycle guide circuit suitable for generating a second clock signal which toggles once in each burst refresh cycle, based on the burst refresh command signal and a precharge signal; a second count circuit suitable for counting the second clock signal and generating a second count code signal; and a control circuit suitable for generating a latch control signal for latching a target address in each burst refresh cycle, based on the first count code signal and the second count code signal.

Abstract: A semiconductor memory apparatus includes a plurality of memory banks and a refresh control circuit. The refresh control circuit, in each plurality of cycles, performs a refresh operation on at least one memory bank of the plurality of memory banks at a first refresh rate, and performs a refresh operation on the other memory banks of the plurality of memory banks at a second refresh rate. The refresh control circuit circulates the at least one memory bank on which the refresh operation is performed at the first refresh rate in each one or more cycles of the plurality of cycles.

Abstract: A semiconductor memory device includes a first count circuit suitable for counting a first clock signal which continuously toggles in each burst refresh cycle, and generating a first count code signal, based on a burst refresh command signal; a cycle guide circuit suitable for generating a second clock signal which toggles once in each burst refresh cycle, based on the burst refresh command signal and a precharge signal; a second count circuit suitable for counting the second clock signal and generating a second count code signal; and a control circuit suitable for generating a latch control signal for latching a target address in each burst refresh cycle, based on the first count code signal and the second count code signal.

Abstract: A semiconductor memory device includes a first count circuit suitable for counting a first clock signal which continuously toggles in each burst refresh cycle, and generating a first count code signal, based on a burst refresh command signal; a cycle guide circuit suitable for generating a second clock signal which toggles once in each burst refresh cycle, based on the burst refresh command signal and a precharge signal; a second count circuit suitable for counting the second clock signal and generating a second count code signal; and a control circuit suitable for generating a latch control signal for latching a target address in each burst refresh cycle, based on the first count code signal and the second count code signal.

Abstract: A semiconductor memory device includes a first count circuit suitable for counting a first clock signal which continuously toggles in each burst refresh cycle, and generating a first count code signal, based on a burst refresh command signal; a cycle guide circuit suitable for generating a second clock signal which toggles once in each burst refresh cycle, based on the burst refresh command signal and a precharge signal; a second count circuit suitable for counting the second clock signal and generating a second count code signal; and a control circuit suitable for generating a latch control signal for latching a target address in each burst refresh cycle, based on the first count code signal and the second count code signal.

Abstract: A semiconductor memory apparatus includes a plurality of memory banks and a refresh control circuit. The refresh control circuit, in each plurality of cycles, performs a refresh operation on at least one memory bank of the plurality of memory banks at a first refresh rate, and performs a refresh operation on the other memory banks of the plurality of memory banks at a second refresh rate. The refresh control circuit circulates the at least one memory bank on which the refresh operation is performed at the first refresh rate in each one or more cycles of the plurality of cycles.

Abstract: A semiconductor memory device includes a first count circuit suitable for counting a first clock signal which continuously toggles in each burst refresh cycle, and generating a first count code signal, based on a burst refresh command signal; a cycle guide circuit suitable for generating a second clock signal which toggles once in each burst refresh cycle, based on the burst refresh command signal and a precharge signal; a second count circuit suitable for counting the second clock signal and generating a second count code signal; and a control circuit suitable for generating a latch control signal for latching a target address in each burst refresh cycle, based on the first count code signal and the second count code signal.