Abstract: A semiconductor device comprising first and second unit cells, the first unit cell comprising a first fin pattern extending in a first direction, a first gate pattern extending in a second direction, and a first contact disposed on a side of the first gate pattern contacting the first fin pattern, the second unit cell comprising a second fin pattern extending in the first direction, a second gate pattern extending in the second direction, and a second contact disposed on a side of the second gate pattern contacting the second fin pattern, wherein the first and second gate patterns are spaced apart and lie on a first straight line extending in the second direction, the first and second contacts are spaced apart and lie on a second straight line extending in the second direction, and a first middle contact is disposed on and connects the first and second contacts.

Abstract: Provided in a semiconductor device including a substrate, an active region upwardly protruding from the substrate, a plurality of active fins upwardly protruding from the active region and extending in a first direction parallel to an upper surface of the substrate, the plurality of active fins being provided in a second direction that is parallel to the upper surface of the substrate and intersects with the first direction, and an isolation structure provided on the substrate, the isolation structure covering a sidewall of the active region and a lower portion of a sidewall of each of the plurality of active fins, wherein a first sidewall of the active region adjacent to a first active fin among the plurality of active fins has a staircase shape, the first active fin being provided on a first edge of the active region in the second direction.

Abstract: A semiconductor device comprising first and second unit cells, the first unit cell comprising a first fin pattern extending in a first direction, a first gate pattern extending in a second direction, and a first contact disposed on a side of the first gate pattern contacting the first fin pattern, the second unit cell comprising a second fin pattern extending in the first direction, a second gate pattern extending in the second direction, and a second contact disposed on a side of the second gate pattern contacting the second fin pattern, wherein the first and second gate patterns are spaced apart and lie on a first straight line extending in the second direction, the first and second contacts are spaced apart and lie on a second straight line extending in the second direction, and a first middle contact is disposed on and connects the first and second contacts.

Abstract: Provided in a semiconductor device including a substrate, an active region upwardly protruding from the substrate, a plurality of active fins upwardly protruding from the active region and extending in a first direction parallel to an upper surface of the substrate, the plurality of active fins being provided in a second direction that is parallel to the upper surface of the substrate and intersects with the first direction, and an isolation structure provided on the substrate, the isolation structure covering a sidewall of the active region and a lower portion of a sidewall of each of the plurality of active fins, wherein a first sidewall of the active region adjacent to a first active fin among the plurality of active fins has a staircase shape, the first active fin being provided on a first edge of the active region in the second direction.

Abstract: A method of manufacturing an extreme ultraviolet (EUV) mask, for use in an EUV exposure process, on a mask substrate includes constructing a first monitoring macro considering an effect caused by a slit used in the EUV exposure process, performing an optical proximity correction (OPC) using a plurality of second monitoring macros, wherein each of the plurality of second monitoring macros is substantially identical to the first monitoring macro, inputting mask tape-out (MTO) design data acquired through the OPC, preparing mask data including at least one of data format conversion, mask process correction (MPC), and job-deck for the MTO design data, and performing EUV exposure (writing) on the mask substrate based on the mask data.

Abstract: A method of manufacturing a semiconductor device includes performing extreme ultraviolet (EUV) lithography that uses a mask for the EUV lithography manufactured by using a design layout on which optical proximity correction (OPC) is performed, and performing the OPC includes dividing respective patterns included in the design layout into partial patterns, classifying the partial patterns into a plurality of partial pattern groups, performing a first OPC on the design layout, and performing a second OPC that is different from the first OPC on the design layout on which the first OPC is performed, wherein performing the first OPC is performed on representative patterns selected from the plurality of partial pattern groups.

Abstract: A semiconductor device comprising first and second unit cells, the first unit cell comprising a first fin pattern extending in a first direction, a first gate pattern extending in a second direction, and a first contact disposed on a side of the first gate pattern contacting the first fin pattern, the second unit cell comprising a second fin pattern extending in the first direction, a second gate pattern extending in the second direction, and a second contact disposed on a side of the second gate pattern contacting the second fin pattern, wherein the first and second gate patterns are spaced apart and lie on a first straight line extending in the second direction, the first and second contacts are spaced apart and lie on a second straight line extending in the second direction, and a first middle contact is disposed on and connects the first and second contacts.

Abstract: An optical proximity correction (OPC) method includes preparing basic data for OPC, measuring with a scanning electron microscope (SEM) an after development inspection (ADI) critical dimension (CD) of a photoresist (PR) pattern with respect to a sample, measuring with the SEM an after cleaning inspection (ACI) CD of a wafer pattern formed using the PR pattern, generating CD data of the sample reflecting PR shrinking caused by the SEM measurement by using the measured ADI CD of the PR pattern and the measured ACI CD of the wafer pattern; and generating an OPC model based on the basic data and the CD data of the sample.

Abstract: An optical proximity correction (OPC) method may include providing a design layout including conductive patterns, determining line end void (LEV)-risk patterns among the conductive patterns, the LEV-risk patterns each having a risk of suffering from poor contact due to an LEV, setting markers including portions of the LEV-risk patterns and portions of the conductive patterns adjacent to the LEV-risk patterns, performing a first OPC on first patterns included in the markers and performing a second OPC on second patterns outside the markers, the second OPC being different from the first OPC, and each of the first OPC and the second OPC being performed a plurality of times, and calculating a cost function of each of the markers. The determining may include comparing risks of occurrence of poor contact in each of the conductive patterns based on a scoring function, and the scoring function may be inversely proportional to a width of each of the conductive patterns.

Abstract: An optical proximity correction (OPC) method may include providing a design layout including conductive patterns, determining line end void (LEV)-risk patterns among the conductive patterns, the LEV-risk patterns each having a risk of suffering from poor contact due to an LEV, setting markers including portions of the LEV-risk patterns and portions of the conductive patterns adjacent to the LEV-risk patterns, performing a first OPC on first patterns included in the markers and performing a second OPC on second patterns outside the markers, the second OPC being different from the first OPC, and each of the first OPC and the second OPC being performed a plurality of times, and calculating a cost function of each of the markers. The determining may include comparing risks of occurrence of poor contact in each of the conductive patterns based on a scoring function, and the scoring function may be inversely proportional to a width of each of the conductive patterns.

Abstract: Provided in a semiconductor device including a substrate, an active region upwardly protruding from the substrate, a plurality of active fins upwardly protruding from the active region and extending in a first direction parallel to an upper surface of the substrate, the plurality of active fins being provided in a second direction that is parallel to the upper surface of the substrate and intersects with the first direction, and an isolation structure provided on the substrate, the isolation structure covering a sidewall of the active region and a lower portion of a sidewall of each of the plurality of active fins, wherein a first sidewall of the active region adjacent to a first active fin among the plurality of active fins has a staircase shape, the first active fin being provided on a first edge of the active region in the second direction.

Abstract: A method of manufacturing a semiconductor device includes performing extreme ultraviolet (EUV) lithography that uses a mask for the EUV lithography manufactured by using a design layout on which optical proximity correction (OPC) is performed, and performing the OPC includes dividing respective patterns included in the design layout into partial patterns, classifying the partial patterns into a plurality of partial pattern groups, performing a first OPC on the design layout, and performing a second OPC that is different from the first OPC on the design layout on which the first OPC is performed, wherein performing the first OPC is performed on representative patterns selected from the plurality of partial pattern groups.

Abstract: A method of manufacturing an extreme ultraviolet (EUV) mask, for use in an EUV exposure process, on a mask substrate includes constructing a first monitoring macro considering an effect caused by a slit used in the EUV exposure process, performing an optical proximity correction (OPC) using a plurality of second monitoring macros, wherein each of the plurality of second monitoring macros is substantially identical to the first monitoring macro, inputting mask tape-out (MTO) design data acquired through the OPC, preparing mask data including at least one of data format conversion, mask process correction (MPC), and job-deck for the MTO design data, and performing EUV exposure (writing) on the mask substrate based on the mask data.

Abstract: The method includes classifying sample pattern data into a standard normal group and a standard weak group based on a first criterion. The method further includes extracting a normal group determination function by calculating an image parameter with respect to each piece of sample pattern data included in the standard normal group, and extracting a weak group determination function by calculating the image parameter with respect to each piece of sample pattern data included in the standard weak group. The method also includes classifying the object pattern data into a normal group and a weak group by calculating the image parameter with respect to object pattern data based on a first proximity between the normal group determination function and the object pattern data and a second proximity between the weak group determination function and the object pattern data.

Abstract: An optical proximity correction (OPC) method includes preparing basic data for OPC, measuring with a scanning electron microscope (SEM) an after development inspection (ADI) critical dimension (CD) of a photoresist (PR) pattern with respect to a sample, measuring with the SEM an after cleaning inspection (ACI) CD of a wafer pattern formed using the PR pattern, generating CD data of the sample reflecting PR shrinking caused by the SEM measurement by using the measured ADI CD of the PR pattern and the measured ACI CD of the wafer pattern; and generating an OPC model based on the basic data and the CD data of the sample.

Abstract: The method includes classifying sample pattern data into a standard normal group and a standard weak group based on a first criterion. The method further includes extracting a normal group determination function by calculating an image parameter with respect to each piece of sample pattern data included in the standard normal group, and extracting a weak group determination function by calculating the image parameter with respect to each piece of sample pattern data included in the standard weak group. The method also includes classifying the object pattern data into a normal group and a weak group by calculating the image parameter with respect to object pattern data based on a first proximity between the normal group determination function and the object pattern data and a second proximity between the weak group determination function and the object pattern data.

Abstract: A semiconductor device, comprising a substrate, a plurality of polysilicon portions formed on the substrate, wherein the polysilicon portions are spaced apart from each other, a plurality of source/drain regions formed in the substrate between adjacent polysilicon portions, and a dielectric layer formed on the polysilicon portions and on the source/drain regions, wherein the dielectric layer includes a cavity filled with conductive material to form a contact area, the contact area overlapping part of a source/drain region and part of a polysilicon portion to electrically connect the polysilicon portion with the source/drain region, and wherein part of the contact area extends below an upper surface of the substrate to contact an implant region with the same doping as the source/drain region. The implant region is next to the source/drain region and includes part of a channel region in the substrate under the polysilicon portion.

Abstract: A method for forming a circuit layout comprises performing process proximity effect modeling based on process proximity effects caused by a sub-layer, wherein the sub-layer comprises an active layer positioned under a gate poly, and wherein performing the process proximity effect modeling includes calculating a pattern density of the sub-layer, incorporating results of the process proximity effect modeling into a modeling algorithm, and performing proximity correction using the results to manipulate a layout of a mask to be used when forming the circuit layout by photolithography.

Abstract: A semiconductor device, comprising a substrate, a plurality of polysilicon portions formed on the substrate, wherein the polysilicon portions are spaced apart from each other, a plurality of source/drain regions formed in the substrate between adjacent polysilicon portions, and a dielectric layer formed on the polysilicon portions and on the source/drain regions, wherein the dielectric layer includes a cavity filled with conductive material to form a contact area, the contact area overlapping part of a source/drain region and part of a polysilicon portion to electrically connect the polysilicon portion with the source/drain region, and wherein part of the contact area extends below an upper surface of the substrate to contact an implant region with the same doping as the source/drain region. The implant region is next to the source/drain region and includes part of a channel region in the substrate under the polysilicon portion.

Abstract: A method for forming a circuit layout comprises performing process proximity effect modeling based on process proximity effects caused by a sub-layer, wherein the sub-layer comprises an active layer positioned under a gate poly, and wherein performing the process proximity effect modeling includes calculating a pattern density of the sub-layer, incorporating results of the process proximity effect modeling into a modeling algorithm, and performing proximity correction using the results to manipulate a layout of a mask to be used when forming the circuit layout by photolithography.