Patents by Inventor Noah Beck

Noah Beck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210132675
    Abstract: A method and apparatus for scrambling and descrambling data in a computer system includes transmitting non-scrambled data from a first high speed inter chip (IP) link circuit located on a first chip to a first serializer/deserializer (SERDES) physical (PHY) circuit located on the first chip, the first high speed link IP indicating the data is not scrambled. The received non-scrambled data is scrambled by the first SERDES PHY circuit and transmitted to a second chip. The received scrambled data is descrambled by a second SERDES PHY circuit located on the second chip. The non-scrambled data is transmitted by the second SERDES PHY circuit to a second high speed link IP circuit located on the second chip to a third circuit for further processing or transmission.
    Type: Application
    Filed: January 15, 2021
    Publication date: May 6, 2021
    Applicants: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Yanfeng Wang, Michael J. Tresidder, Kevin M. Lepak, Larry David Hewitt, Noah Beck
  • Patent number: 10895901
    Abstract: A method and apparatus for scrambling and descrambling data in a computer system includes transmitting non-scrambled data from a first high speed inter chip (IP) link circuit located on a first chip to a first serializer/deserializer (SERDES) physical (PHY) circuit located on the first chip, the first high speed link IP indicating the data is not scrambled. The received non-scrambled data is scrambled by the first SERDES PHY circuit and transmitted to a second chip. The received scrambled data is descrambled by a second SERDES PHY circuit located on the second chip. The non-scrambled data is transmitted by the second SERDES PHY circuit to a second high speed link IP circuit located on the second chip to a third circuit for further processing or transmission.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: January 19, 2021
    Assignees: ADVANCED MICRO DEVICES INC., ATI TECHNOLOGIES ULC
    Inventors: Yanfeng Wang, Michael J. Tresidder, Kevin M. Lepak, Larry David Hewitt, Noah Beck
  • Patent number: 9696790
    Abstract: Processor power may be managed by executing state storage and power gating instructions after receiving an idle indication. The idle indication may be received while the processor is executing instructions in a first mode, and the processor may execute the state storage and power gating instructions in a second mode. The state storage and power gating instructions may be inaccessible to the processor when operating in the first mode.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: July 4, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Noah Beck, John D. Wilkes, Jr., Francisco Leonel Duran
  • Publication number: 20160116970
    Abstract: Processor power may be managed by executing state storage and power gating instructions after receiving an idle indication. The idle indication may be received while the processor is executing instructions in a first mode, and the processor may execute the state storage and power gating instructions in a second mode. The state storage and power gating instructions may be inaccessible to the processor when operating in the first mode.
    Type: Application
    Filed: October 24, 2014
    Publication date: April 28, 2016
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Noah Beck, John D. Wilkes, JR., Francisco Leonel Duran