Patents by Inventor Noah Seth Clay

Noah Seth Clay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FORMING SEMICONDUCTOR-SUPERCONDUCTOR HYBRID DEVICES WITH A HORIZONTALLY-CONFINED CHANNEL
    Publication number: 20240065113
    Abstract: Methods of forming semiconductor-superconductor hybrid devices with a horizontally-confined channel are described. An example method includes forming a first isolated semiconductor heterostructure and a second isolated semiconductor heterostructure. The method further includes forming a left gate adjacent to a first side of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure. The method further includes forming a right gate adjacent to a second side, opposite to the first side, of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure, where a top surface of each of the left gate and the right gate is offset vertically from a selected surface of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure by a predetermined offset amount.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 22, 2024
    Inventors: Geoffrey Charles GARDNER, Sergei Vyatcheslavovich GRONIN, Flavio GRIGGIO, Raymond Leonard KALLAHER, Noah Seth CLAY, Michael James MANFRA
  • Forming semiconductor-superconductor hybrid devices with a horizontally-confined channel
    Patent number: 11849639
    Abstract: Methods of forming semiconductor-superconductor hybrid devices with a horizontally-confined channel are described. An example method includes forming a first isolated semiconductor heterostructure and a second isolated semiconductor heterostructure. The method further includes forming a left gate adjacent to a first side of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure. The method further includes forming a right gate adjacent to a second side, opposite to the first side, of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure, where a top surface of each of the left gate and the right gate is offset vertically from a selected surface of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure by a predetermined offset amount.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: December 19, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey Charles Gardner, Sergei Vyatcheslavovich Gronin, Flavio Griggio, Raymond Leonard Kallaher, Noah Seth Clay, Michael James Manfra