Patents by Inventor Noam Bloch

Noam Bloch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220232072
    Abstract: A network device includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to connect to a host including a host processor running a client process. The processing circuitry is configured to receive packets originating from a peer process, to identify, in at least some of the received packets, application level information that is exchanged between the client process and the peer process, and to initiate reporting of one or more of the received packets to the client process, based on the application level information.
    Type: Application
    Filed: January 19, 2021
    Publication date: July 21, 2022
    Inventors: Or Gerlitz, Noam Bloch, Gal Yefet
  • Publication number: 20220158772
    Abstract: A method for data transfer includes transmitting a sequence of data packets from a first computer over a network to a second computer in a single RDMA data transfer transaction. Upon receipt of a second packet in the sequence without previously having received the first packet, the second computer sends a NAK packet over the network to the first computer, indicating that the first packet was not received. A retransmission mode is selected responsively to the type of the transaction, such that when the transaction is of a first type, the first packet is retransmitted from the first computer to the second computer in response to the NAK packet without retransmitting the second packet, and when the transaction is of a second type, both the first and second packets are retransmitted from the first computer to the second computer in response to the NAK packet.
    Type: Application
    Filed: December 1, 2020
    Publication date: May 19, 2022
    Inventors: Idan Burstein, Roee Moyal, Ariel Shahar, Noam Bloch, Ran Koren
  • Patent number: 11296988
    Abstract: A network adapter includes a receive (Rx) pipeline, a transmit (Tx) pipeline and congestion management circuitry. The Rx pipeline is configured to receive packets sent over a network by a peer network adapter, and to process the received packets. The Tx pipeline is configured to transmit packets to the peer network adapter over the network. The congestion management circuitry is configured to receive, from the Tx pipeline and from the Rx pipeline, Congestion-Control (CC) events derived from at least some of the packets exchanged with the peer network adapter, to exchange user-programmable congestion control packets with the peer network adapter, and to mitigate a congestion affecting one or more of the packets responsively to the CC events and the user-programmable congestion control packets.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: April 5, 2022
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Yuval Shpigelman, Idan Burstein, Noam Bloch, Reut Zuck, Roee Moyal
  • Patent number: 11277455
    Abstract: A method including configuring a transmit process to store information including a queue of packets to be transmitted, the queue defining transmit process packets to be transmitted, each packet associated with a transmission time, and configuring a synchronization process to receive from the transmit process at least some of the information. The synchronization process performs one of: A) accessing a dummy send queue and a completion queue, and transmitting one or more of the transmit process packets in accordance with a completion queue entry in the completion queue, and B) sends a doorbell to transmission hardware at a time when at least one of the transmit process packets is to be transmitted, the synchronization process including a master queue configured to store transmission entries, each transmission entry including a transmit process indicator and an indication of transmit process packets to be transmitted. Related apparatus and methods are also described.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: March 15, 2022
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Dotan David Levi, Alex Vainman, Natan Manevich, Nir Nitzani, Ilan Smith, Richard Hastie, Noam Bloch, Lior Narkis, Rafi Weiner
  • Patent number: 11258885
    Abstract: One embodiment includes a network device, including hardware parsers to receive data of a header section of a packet, the header section including respective headers, parser configuration registers to store a default parsing configuration data set, wherein at least one of the hardware parsers is configured to parse at least one of the headers responsively to the default parsing configuration data set, yielding first parsed data, a packet processing engine to select a selected parsing configuration data set from a selection of parsing configuration data sets responsively to the first parsed data, cause loading of the selected parsing configuration data set into the parser configuration registers, and wherein ones of the hardware parsers are configured to parse respective ones of the headers responsively to the selected parsing configuration data set, yielding second parsed data, and process the packet responsively to the second parsed data.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: February 22, 2022
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Avi Urman, Lior Narkis, Noam Bloch
  • Publication number: 20220045844
    Abstract: In one embodiment, data communication apparatus includes a network interface for connection to a network and configured to receive a sequence of data packets from a remote device over the network, the sequence including data blocks, ones of the data blocks having block boundaries that are not aligned with payload boundaries of the packets, and packet processing circuitry to cryptographically process the data blocks using a block cipher so as to write corresponding cryptographically processed data blocks to a memory, while holding segments of respective ones of the received data blocks in the memory, such that the packet processing circuitry stores a first segment of a data block of a first packet in the memory until a second packet is received, and then cryptographically processes the first and second segments together so as to write a corresponding cryptographically processed data block to the memory.
    Type: Application
    Filed: April 19, 2021
    Publication date: February 10, 2022
    Inventors: Miriam Menes, Noam Bloch, Adi Menachem, Idan Burstein, Ariel Shahar, Maxim Fudim
  • Publication number: 20220029854
    Abstract: A method in which a plurality of process are configured to hold a block of data destined for other processes, with data repacking circuitry including receiving circuitry configured to receive at least one block of data from a source process of the plurality of processes, the repacking circuitry configured to repack received data in accordance with at least one destination process of the plurality of processes, and sending circuitry configured to send the repacked data to the at least one destination process of the plurality of processes, receiving a set of data for all-to-all data exchange, the set of data being configured as a matrix, the matrix being distributed among the plurality of processes, and transposing the data by each of the plurality of processes sending matrix data from the process to the repacking circuitry, and the repacking circuitry receiving, repacking, and sending the resulting matrix data to destination processes.
    Type: Application
    Filed: October 7, 2021
    Publication date: January 27, 2022
    Inventors: Richard Graham, Lion Levi, Gil Bloch, Daniel Marcovitch, Noam Bloch, Yong Qin, Yaniv Blumenfeld, Eitan Zahavi
  • Patent number: 11196586
    Abstract: A method in which a plurality of process are configured to hold a block of data destined for other processes, with data repacking circuitry including receiving circuitry configured to receive at least one block of data from a source process of the plurality of processes, the repacking circuitry configured to repack received data in accordance with at least one destination process of the plurality of processes, and sending circuitry configured to send the repacked data to the at least one destination process of the plurality of processes, receiving a set of data for all-to-all data exchange, the set of data being configured as a matrix, the matrix being distributed among the plurality of processes, and transposing the data by each of the plurality of processes sending matrix data from the process to the repacking circuitry, and the repacking circuitry receiving, repacking, and sending the resulting matrix data to destination processes.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: December 7, 2021
    Assignee: MELLANOX TECHNOLOGIES TLV LTD.
    Inventors: Richard Graham, Lion Levi, Gil Bloch, Daniel Marcovitch, Noam Bloch, Yong Qin, Yaniv Blumenfeld, Eitan Zahavi
  • Publication number: 20210344600
    Abstract: A network adapter includes a host interface, a network interface, a memory and packet processing circuitry. The memory holds a shared buffer and multiple queues allocated to the multiple host processors. The packet processing circuitry is configured to receive from the network interface data packets destined to the host processors, to store payloads of at least some of the data packets in the shared buffer, to distribute headers of at least some of the data packets to the queues, to serve the data packets to the host processors by applying scheduling among the queues, to detect congestion in the data packets destined to a given host processor among the host processors, and, in response to the detected congestion, to mitigate the congestion in the data packets destined to the given host processor, while retaining uninterrupted processing of the data packets destined to the other host processors.
    Type: Application
    Filed: May 4, 2020
    Publication date: November 4, 2021
    Inventors: Avi Urman, Lior Narkis, Noam Bloch, Eyal Srebro, Shay Aisman
  • Patent number: 11102129
    Abstract: A network adapter includes circuitry and one or more ports. The ports connect to a communication network including multiple network elements. The circuitry accesses outbound messages that are pending to be sent over the communication network to multiple remote nodes via the ports. At least some of the outbound messages request the remote nodes to send respective amounts of data back to the network adapter. Based on the amounts of data requested by the outbound messages, the circuitry forecasts a bandwidth of inbound response traffic, which is expected to traverse a selected network element in response to the outbound messages toward the network adapter, determines a schedule for transmitting the outbound messages to the remote nodes so that the forecasted bandwidth meets a bandwidth supported by the selected network element, and transmits the outbound messages to the remote nodes in accordance with the determined schedule.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: August 24, 2021
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Idan Burstein, Noam Bloch, Roee Moyal, Ariel Shahar, Yamin Friedman, Yuval Shpigelman
  • Patent number: 11088966
    Abstract: A network adapter includes a host interface and circuitry. The host interface is configured to connect locally between the network adapter and a host via a bus. The circuitry is configured to receive from one or more source nodes, over a communication network to which the network adapter is coupled, multiple packets destined to the host, and temporarily store the received packets in a queue of the network adapter, to send the stored packets from the queue to the host over the bus, to monitor a performance attribute of the bus, and in response to detecting, based at least on the monitored performance attribute, an imminent overfilling state of the queue, send a congestion notification to at least one of the source nodes from which the received packets originated.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: August 10, 2021
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Adi Menachem, Alex Shpiner, Noam Bloch, Eitan Zahavi, Idan Burstein, Dror Bohrer, Roee Moyal
  • Publication number: 20210243121
    Abstract: A communication apparatus includes a host interface, connected to a peripheral component bus so as to communicate with a CPU and a memory of a host computer. A network interface is connected to a network. Packet processing circuitry is configured to receive from a first interface a data packet including a set of one or more headers that include header fields having respective values, to identify, responsively to at least one of the header fields, a corresponding entry in a header modification table that specifies a header modification operation, to modify the set of headers in accordance with the header modification operation, to check whether the entry specifies an additional header modification operation, to output the modified set of headers if the entry does not specify an additional header modification operation, and, if the entry specifies an additional header modification operation, to feed-back the modified set of headers.
    Type: Application
    Filed: February 4, 2020
    Publication date: August 5, 2021
    Inventors: Avi Urman, Lior Narkis, Noam Bloch
  • Publication number: 20210218808
    Abstract: An apparatus includes one or more ports for connecting to a communication network, processing circuitry and a message aggregation circuit (MAC). The processing circuitry is configured to communicate messages over the communication network via the one or more ports. The MAC is configured to receive messages, which originate in one or more source processes and are destined to one or more destination processes, to aggregate two or more of the messages that share a common destination into an aggregated message, and to send the aggregated message using the processing circuitry over the communication network.
    Type: Application
    Filed: January 13, 2021
    Publication date: July 15, 2021
    Inventors: Richard Graham, Lion Levi, Daniel Marcovitch, Larry R. Dennison, Aviad Levy, Noam Bloch, Gil Bloch
  • Patent number: 11055222
    Abstract: Computing apparatus includes a central processing unit (CPU), including at least one core and a cache in physical proximity to the at least one core, with a system memory and a bus connecting the CPU to the memory. A peripheral device is connected to the bus and is configured to write data items via the bus to a buffer in the system memory and to write respective completion reports to the system memory upon writing the data items to the buffer. The peripheral device is configured to detect that the CPU has read a first completion report from the system memory and then read context metadata associated with the first completion report from a given address in the system memory, and is further configured, upon writing a second completion report subsequent to the first completion report and associated with the same context metadata, to stash the second completion report and the context metadata from the given address to the cache.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: July 6, 2021
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Ilan Pardo, Noam Bloch
  • Publication number: 20210176345
    Abstract: One embodiment includes a network device, including hardware parsers to receive data of a header section of a packet, the header section including respective headers, parser configuration registers to store a default parsing configuration data set, wherein at least one of the hardware parsers is configured to parse at least one of the headers responsively to the default parsing configuration data set, yielding first parsed data, a packet processing engine to select a selected parsing configuration data set from a selection of parsing configuration data sets responsively to the first parsed data, cause loading of the selected parsing configuration data set into the parser configuration registers, and wherein ones of the hardware parsers are configured to parse respective ones of the headers responsively to the selected parsing configuration data set, yielding second parsed data, and process the packet responsively to the second parsed data.
    Type: Application
    Filed: December 10, 2019
    Publication date: June 10, 2021
    Inventors: Avi Urman, Lior Narkis, Noam Bloch
  • Publication number: 20210152474
    Abstract: A network adapter includes a receive (Rx) pipeline, a transmit (Tx) pipeline and congestion management circuitry. The Rx pipeline is configured to receive packets sent over a network by a peer network adapter, and to process the received packets. The Tx pipeline is configured to transmit packets to the peer network adapter over the network. The congestion management circuitry is configured to receive, from the Tx pipeline and from the Rx pipeline, Congestion-Control (CC) events derived from at least some of the packets exchanged with the peer network adapter, to exchange user-programmable congestion control packets with the peer network adapter, and to mitigate a congestion affecting one or more of the packets responsively to the CC events and the user-programmable congestion control packets.
    Type: Application
    Filed: August 6, 2020
    Publication date: May 20, 2021
    Inventors: Yuval Shpigelman, Idan Burstein, Noam Bloch, Reut Zuck, Roee Moyal
  • Publication number: 20210111996
    Abstract: A system includes a host processor, which has a host memory and is coupled to store data in a non-volatile memory in accordance with a storage protocol. A network interface controller (NIC) receives data packets conveyed over a packet communication network from peer computers containing, in payloads of the data packets, data records that encode data in accordance with the storage protocol for storage in the non-volatile memory. The NIC processes the data records in the data packets that are received in order in each flow from a peer computer and extracts and writes the data to the host memory, and when a data packet arrives out of order, writes the data packet to the host memory without extracting the data and processes the data packets in the flow so as to recover context information for use in processing the data records in subsequent data packets in the flow.
    Type: Application
    Filed: December 1, 2020
    Publication date: April 15, 2021
    Inventors: Boris Pismenny, Miriam Menes, Idan Burstein, Liran Liss, Noam Bloch, Ariel Shahar
  • Publication number: 20210073130
    Abstract: Computing apparatus includes a central processing unit (CPU), including at least one core and a cache in physical proximity to the at least one core, with a system memory and a bus connecting the CPU to the memory. A peripheral device is connected to the bus and is configured to write data items via the bus to a buffer in the system memory and to write respective completion reports to the system memory upon writing the data items to the buffer. The peripheral device is configured to detect that the CPU has read a first completion report from the system memory and then read context metadata associated with the first completion report from a given address in the system memory, and is further configured, upon writing a second completion report subsequent to the first completion report and associated with the same context metadata, to stash the second completion report and the context metadata from the given address to the cache.
    Type: Application
    Filed: September 10, 2019
    Publication date: March 11, 2021
    Inventors: Ilan Pardo, Noam Bloch
  • Patent number: 10887252
    Abstract: A network interface device is connected to a host computer by having a memory controller, and a scatter-gather offload engine linked to the memory controller. The network interface device prepares a descriptor including a plurality of specified memory locations in the host computer, incorporates the descriptor in exactly one upload packet, transmits the upload packet to the scatter-gather offload engine via the uplink, invokes the scatter-gather offload engine to perform memory access operations cooperatively with the memory controller at the specified memory locations of the descriptor, and accepts results of the memory access operations.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: January 5, 2021
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Dror Bohrer, Noam Bloch, Peter Paneah, Richard Graham
  • Patent number: 10841243
    Abstract: A network interface controller that is connected to a host and a packet communications network. The network interface controller includes electrical circuitry configured as a packet processing pipeline with a plurality of stages. It is determined in the network interface controller that at least a portion of the stages of the pipeline are acceleration-defined stages. Packets are processed in the pipeline by transmitting data to an accelerator from the acceleration-defined stages, performing respective acceleration tasks on the transmitted data in the accelerator, and returning processed data from the accelerator to receiving stages of the pipeline.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: November 17, 2020
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Dotan Levi, Liran Liss, Haggai Eran, Noam Bloch, Idan Burstein, Lior Narkis, Avraham Ganor