Abstract: Lighting systems combine UV-A and white light with an adjustable CCT value so that any adverse effects from the UV-A radiation are mitigated—that is, tunable adjustments to the output of the non-UV LEDs, or to all of the LEDs, result in an overall mixed output conforming to a target CCT value.

Abstract: A packet processing architecture includes a plurality of packet processing stages, wherein at least one of the packet processing stages includes multiple next processing stage modules that are operably coupled to respective further processing stages, wherein the multiple next processing stage modules are dynamically configurable.

Abstract: The embodiments described herein provide systems and methods for recovering resources in processing devices. Specifically, the embodiments described herein provide techniques for recovering leaked resources allocated to hardware engines in a hardware processing core. As one example, the recovery of resources allocated to hardware engines can be facilitated by making a specified register available to monitoring software. When leaked or otherwise stuck resources are identified, the monitoring software can set the register to trigger the recovery of those resources. This recovery of resources can be then performed by stopping the execution of processes in the hardware engines, invalidating the resources previously allocated to the hardware engines, initializing the resources, and starting the handling of new processes in the hardware engines. This process effectively recovers those resources, and allows those hardware engines to quickly resume operations.

Abstract: In a pipelined network processor, a first stage in the pipeline is responsive to receipt of a pause indication from a third stage. The pause indication is associated with one of a plurality of ports and priority classes of frames advancing through the pipeline. The first stage asserts a hold indication to a second stage in response to the pause indication. The second stage is responsive to the hold indication by marking frames associated with the one of a plurality of ports and priority classes as they arrive from the pipeline at the second stage by returning them to the first stage interface instead of transmitting them to the third stage. The marked frames are stored in memory external to the network processor.

Abstract: In a pipelined network processor, a first stage in the pipeline is responsive to receipt of a pause indication from a third stage. The pause indication is associated with one of a plurality of ports and priority classes of frames advancing through the pipeline. The first stage asserts a hold indication to a second stage in response to the pause indication. The second stage is responsive to the hold indication by marking frames associated with the one of a plurality of ports and priority classes as they arrive from the pipeline at the second stage by returning them to the first stage interface instead of transmitting them to the third stage. The marked frames are stored in memory external to the network processor.

Abstract: The embodiments described herein provide systems and methods for recovering resources in processing devices. Specifically, the embodiments described herein provide techniques for recovering leaked resources allocated to hardware engines in a hardware processing core. As one example, the recovery of resources allocated to hardware engines can be facilitated by making a specified register available to monitoring software. When leaked or otherwise stuck resources are identified, the monitoring software can set the register to trigger the recovery of those resources. This recovery of resources can be then performed by stopping the execution of processes in the hardware engines, invalidating the resources previously allocated to the hardware engines, initializing the resources, and starting the handling of new processes in the hardware engines. This process effectively recovers those resources, and allows those hardware engines to quickly resume operations.

Abstract: A packet processing architecture includes a plurality of packet processing stages, wherein at least one of the packet processing stages includes multiple next processing stage modules that are operably coupled to respective further processing stages, wherein the multiple next processing stage modules are dynamically configurable.