Patents by Inventor Noam Eshel

Noam Eshel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10659714
    Abstract: An image sensor including a pixel circuit and an active reset circuit. The pixel circuit includes a light sensing element, a storage node selectively connected to the light sensing element, an output transistor configured to, during a readout operation, output a signal that is based on a potential of the charge storage node to an output line, and a selection transistor that controls the readout operation. The active reset circuit includes a first current path and a second current path, the first current path extending from a power supply node to the output line via the selection transistor and the output transistor, and the second current path extending from the power supply node to the output line via a first transistor and a second transistor. The active reset circuit is configured to, when the selection transistor and the first transistor are both ON, set a potential of the charge storage node based on a potential of a gate of the second transistor.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: May 19, 2020
    Assignee: Sony Corporation
    Inventors: Thomas Ayers, Jinsuk Kang, Brian Carey, Noam Eshel, Frederick Brady
  • Patent number: 10594967
    Abstract: A sample-and-hold-circuit includes an amplifier transistor, a resistor connected between a source terminal of the amplifier and a voltage, a first switch connected in parallel with the resistor, and a second switch connected between a gate terminal of the amplifier transistor and the voltage. When the first switch is closed and the second switch is open, the amplifier transistor is in an inversion mode; and when the first switch is open and the second switch is closed, the amplifier transistor is in an accumulation mode.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: March 17, 2020
    Assignee: Sony Corporation
    Inventors: Noam Eshel, Golan Zeituni
  • Patent number: 10531028
    Abstract: The present technology is concerned with a solid-state imaging device, a method of driving a solid-state imaging device, and an electronic device which are capable of reducing power supply noise of a pixel signal with a single-ended circuit arrangement. The solid-state imaging device includes a pixel section including a plurality of unit pixels disposed for photoelectric transduction, a power supply noise detector detecting a noise component from a power supply used to energize the unit pixels and outputting a single-ended canceling signal including a canceling component for canceling the noise component, a sample and hold section configured to sample single-ended pixel signals output from the unit pixels and hold and output pixel signals representing the sampled pixel signals from which the noise component has been removed on the basis of the canceling signal, and an A/D converter performing A/D conversion on the pixel signals that have been held.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: January 7, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Kouji Matsuura, Noam Eshel
  • Publication number: 20190356877
    Abstract: An image sensor comprises a plurality of image pixel circuits arranged in an array; image processing circuitry including a sample-and-hold circuit configured to receive a first reference voltage and an analog-to-digital converter configured to receive a second reference voltage; and a reference adjustment circuit configured to selectively adjust the first reference voltage and/or the second reference voltage, thereby to match an operating range of the sample-and-hold circuit with an operating range of the analog-to-digital converter, based on a measurement signal.
    Type: Application
    Filed: August 14, 2018
    Publication date: November 21, 2019
    Inventors: Noam Eshel, Golan Zeituni
  • Publication number: 20190356874
    Abstract: A sample-and-hold circuit comprises a sampling capacitor; an amplifier transistor; and a noise reduction circuit including an integration capacitor and a feedback capacitor, the noise reduction circuit being configured to reduce noise via a four-phase operation including: an auto-zero phase in which the feedback capacitor is discharged, a feedback phase in which a gate voltage of the amplifier transistor is partially compensated through the feedback capacitor, an integration phase in which the integration capacitor is charged, and a feedforward phase in which the gate voltage of the amplifier transistor is fully compensated by a voltage on the integration capacitor through the feedback capacitor.
    Type: Application
    Filed: August 8, 2018
    Publication date: November 21, 2019
    Inventors: Noam Eshel, Golan Zeituni
  • Patent number: 10462397
    Abstract: A sample-and-hold circuit comprises a sampling capacitor; an amplifier transistor; and a noise reduction circuit including an integration capacitor and a feedback capacitor, the noise reduction circuit being configured to reduce noise via a four-phase operation including: an auto-zero phase in which the feedback capacitor is discharged, a feedback phase in which a gate voltage of the amplifier transistor is partially compensated through the feedback capacitor, an integration phase in which the integration capacitor is charged, and a feedforward phase in which the gate voltage of the amplifier transistor is fully compensated by a voltage on the integration capacitor through the feedback capacitor.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: October 29, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Noam Eshel, Golan Zeituni
  • Patent number: 10402198
    Abstract: A signal processing device comprising at least one control unit arranged to receive at least one pack-insert instruction, decode the received at least one pack-insert instruction, and output at least one pack-insert control signal in accordance with the received pack-insert instruction. The signal processing device further comprising at least one pack-insert component arranged to receive at least a first data block to be inserted into a sequence of data blocks to be output to at least one destination register, receive a plurality of further data blocks to be packed within the sequence of data blocks to be output to the at least one destination register, arrange the at least first data block and the plurality of further data blocks into a sequence of data blocks based at least partly on the at least one pack-insert control signal, and output the sequence of data blocks.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: September 3, 2019
    Assignee: NXP USA, Inc.
    Inventors: Avi Gal, Fabrice Aidan, Noam Eshel-Goldman, Roy Glasner, Dmitry Lachover, Itay Peled
  • Publication number: 20190089918
    Abstract: An image sensor including a pixel circuit and an active reset circuit. The pixel circuit includes a light sensing element, a storage node selectively connected to the light sensing element, an output transistor configured to, during a readout operation, output a signal that is based on a potential of the charge storage node to an output line, and a selection transistor that controls the readout operation. The active reset circuit includes a first current path and a second current path, the first current path extending from a power supply node to the output line via the selection transistor and the output transistor, and the second current path extending from the power supply node to the output line via a first transistor and a second transistor. The active reset circuit is configured to, when the selection transistor and the first transistor are both ON, set a potential of the charge storage node based on a potential of a gate of the second transistor.
    Type: Application
    Filed: October 1, 2018
    Publication date: March 21, 2019
    Inventors: Thomas Ayers, Jinsuk Kang, Brian Carey, Noam Eshel, Frederick Brady
  • Patent number: 10110841
    Abstract: An image sensor including a pixel circuit and an active reset circuit. The pixel circuit includes a light sensing element, a storage node selectively connected to the light sensing element, an output transistor configured to, during a readout operation, output a signal that is based on a potential of the charge storage node to an output line, and a selection transistor that controls the readout operation. The active reset circuit includes a first current path and a second current path, the first current path extending from a power supply node to the output line via the selection transistor and the output transistor, and the second current path extending from the power supply node to the output line via a first transistor and a second transistor. The active reset circuit is configured to, when the selection transistor and the first transistor are both ON, set a potential of the charge storage node based on a potential of a gate of the second transistor.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: October 23, 2018
    Assignee: Sony Corporation
    Inventors: Thomas Ayers, Jinsuk Kang, Brian Carey, Noam Eshel, Frederick Brady
  • Publication number: 20180234649
    Abstract: The present technology is concerned with a solid-state imaging device, a method of driving a solid-state imaging device, and an electronic device which are capable of reducing power supply noise of a pixel signal with a single-ended circuit arrangement. The solid-state imaging device includes a pixel section including a plurality of unit pixels disposed for photoelectric transduction, a power supply noise detector detecting a noise component from a power supply used to energize the unit pixels and outputting a single-ended canceling signal including a canceling component for canceling the noise component, a sample and hold section configured to sample single-ended pixel signals output from the unit pixels and hold and output pixel signals representing the sampled pixel signals from which the noise component has been removed on the basis of the canceling signal, and an A/D converter performing A/D conversion on the pixel signals that have been held.
    Type: Application
    Filed: August 5, 2016
    Publication date: August 16, 2018
    Applicant: Sony Semiconductor Solutions Corporation
    Inventors: Kouji Matsuura, Noam Eshel
  • Patent number: 10051224
    Abstract: An image processing circuit includes a first dual sample-and-hold circuit that samples a first data and a second data from a first pixel, a second dual sample-and-hold circuit that samples a third data and a fourth data from a second pixel, a voltage-to-current circuit including a resistor and a current source, that receives the first data and the second data to output a first difference data, and that receives the third data and the fourth data to output a second difference data; and an analog-to-digital converter that converts the first and second difference data from an analog form to a digital form.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: August 14, 2018
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Noam Eshel, Golan Zeituni
  • Patent number: 10026497
    Abstract: A sample-and-hold circuit includes a first transistor; a second transistor disposed between a gate electrode and a drain electrode of the first transistor; a sampling capacitor, an electrode of the sampling capacitor being connected to the gate electrode of the first transistor; and a first current source connected to the drain electrode of the first transistor, where a gate electrode of the second transistor receives a gate control signal. A minimum voltage of the gate control signal is Vth2+Vsat2+Vth1+Vsat1, where Vth1 is a threshold voltage of the first transistor, Vsat1 is a saturation voltage of the first transistor, Vth2 is a threshold voltage of the second transistor, and Vsat2 is a saturation voltage of the second transistor.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: July 17, 2018
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Noam Eshel, Golan Zeituni, Zvika Lupu
  • Patent number: 10008283
    Abstract: A sample-and-hold circuit includes a sampling capacitor, a first transistor, a first switch between a gate electrode and a source electrode of the first transistor, a current source connected to the source electrode of the first transistor, and a resistive element and a second switch connected in parallel between a drain electrode of the first transistor and a predetermined voltage. The resistive element may include a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor, or may include multiple transistor banks connected in parallel, each including a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor. The gate control signal may originate from a circuit including a state machine.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: June 26, 2018
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Noam Eshel, Amit Sokolover, Golan Zeituni
  • Publication number: 20180160063
    Abstract: A sample-and-hold-circuit includes an amplifier transistor, a resistor connected between a source terminal of the amplifier and a voltage, a first switch connected in parallel with the resistor, and a second switch connected between a gate terminal of the amplifier transistor and the voltage. When the first switch is closed and the second switch is open, the amplifier transistor is in an inversion mode; and when the first switch is open and the second switch is closed, the amplifier transistor is in an accumulation mode.
    Type: Application
    Filed: February 2, 2018
    Publication date: June 7, 2018
    Inventors: Noam Eshel, Golan Zeituni
  • Patent number: 9930274
    Abstract: A sample-and-hold-circuit includes an amplifier transistor, a resistor connected between a source terminal of the amplifier and a voltage, a first switch connected in parallel with the resistor, and a second switch connected between a gate terminal of the amplifier transistor and the voltage. When the first switch is closed and the second switch is open, the amplifier transistor is in an inversion mode; and when the first switch is open and the second switch is closed, the amplifier transistor is in an accumulation mode.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: March 27, 2018
    Assignee: Sony Corporation
    Inventors: Noam Eshel, Golan Zeituni
  • Publication number: 20180007294
    Abstract: A sample-and-hold-circuit includes an amplifier transistor, a resistor connected between a source terminal of the amplifier and a voltage, a first switch connected in parallel with the resistor, and a second switch connected between a gate terminal of the amplifier transistor and the voltage. When the first switch is closed and the second switch is open, the amplifier transistor is in an inversion mode; and when the first switch is open and the second switch is closed, the amplifier transistor is in an accumulation mode.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Noam Eshel, Golan Zeituni
  • Patent number: 9826180
    Abstract: An image processing circuit comprises a first sample-and-hold circuit that samples a first data from a pixel; a second sample-and-hold circuit that samples a second data from the pixel; a voltage-to-current circuit that includes a resistor and a current source, and receives the first data and the second data to output a difference data; and a black sun spot determination circuit. The black sun spot determination circuit compares a first VSL level at a first time with a second VSL level at a second time, both from the second sample-and-hold circuit, and determines the presence of a black sun spot based on a difference between the first and second level.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: November 21, 2017
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Noam Eshel, Golan Zeituni
  • Publication number: 20170323686
    Abstract: A sample-and-hold circuit includes a first transistor; a second transistor disposed between a gate electrode and a drain electrode of the first transistor; a sampling capacitor, an electrode of the sampling capacitor being connected to the gate electrode of the first transistor; and a first current source connected to the drain electrode of the first transistor, where a gate electrode of the second transistor receives a gate control signal. A minimum voltage of the gate control signal is Vth2+Vsat2+Vth1+Vsat1, where Vth1 is a threshold voltage of the first transistor, Vsat1 is a saturation voltage of the first transistor, Vth2 is a threshold voltage of the second transistor, and Vsat2 is a saturation voltage of the second transistor.
    Type: Application
    Filed: July 7, 2017
    Publication date: November 9, 2017
    Inventors: NOAM ESHEL, GOLAN ZEITUNI, ZVIKA LUPU
  • Publication number: 20170309347
    Abstract: A sample-and-hold circuit includes a sampling capacitor, a first transistor, a first switch between a gate electrode and a source electrode of the first transistor, a current source connected to the source electrode of the first transistor, and a resistive element and a second switch connected in parallel between a drain electrode of the first transistor and a predetermined voltage. The resistive element may include a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor, or may include multiple transistor banks connected in parallel, each including a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor. The gate control signal may originate from a circuit including a state machine.
    Type: Application
    Filed: June 22, 2017
    Publication date: October 26, 2017
    Inventors: Noam Eshel, Amit Sokolover, Golan Zeituni
  • Patent number: 9780129
    Abstract: A sample-and-hold circuit having an error correction circuit portion that compensates for charge injection and noise. The error correction circuit portion includes an error-current-accumulating capacitor and a feedback circuit. The error-correction circuit performs error correction during a sampling operation by accumulating, at the error-current-accumulating capacitor, an error current output from an amplifier of the sample-and-hold circuit, and then applying, via the feedback circuit, a voltage boost to an input of the amplifier. The magnitude of the voltage boost depends on a voltage of the error-current-accumulating capacitor, and on various design parameters of the components of the circuit. By appropriately setting the design parameters, the magnitude of the fed-back voltage boost can be made to cancel out error due to charge injection and noise.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: October 3, 2017
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Noam Eshel