Abstract: An image sensor assembly includes a pixel circuit including a charge storage structure and an amplification transistor. A load path of the amplification transistor is between an amplifier drain line and a pixel output node. A potential at a storage node of the charge storage structure controls the amplification transistor. An amplifier drain circuit is configured to pass a low potential to the amplifier drain line in a reset period and a high potential in a readout period. A transition from the low potential to the high potential is not before an end of the reset period and prior to a start of the readout period.

Abstract: It makes it easier to reduce the line capacitance of vertical signal lines in a solid-state image sensor in which signals are output via the vertical signal lines. The solid-state image sensor is provided with a logic circuit, a pixel circuit, and a negative capacitance circuit. In the solid-state image sensor, the logic circuit processes an analog signal. Also, in the solid-state image sensor, the pixel circuit generates an analog signal by photoelectric conversion, and outputs the analog signal to the logic circuit via a predetermined signal line. In the solid-state image sensor, the negative capacitance circuit is connected to the predetermined signal line.

Abstract: An image sensor and electronic apparatus comprise a pixel circuit configured to generate an analog signal; a vertical signal line configured to convey the analog signal from the pixel circuit; an analog amplifier circuit configured to receive the analog signal via the vertical signal line and generate an amplified signal; and a tail current boost circuit configured to modify an instantaneous gain bandwidth product of the analog amplifier circuit by temporarily modifying a tail current of the analog amplifier circuit.

Abstract: It makes it easier to reduce the line capacitance of vertical signal lines in a solid-state image sensor in which signals are output via the vertical signal lines. The solid-state image sensor is provided with a logic circuit, a pixel circuit, and a negative capacitance circuit. In the solid-state image sensor, the logic circuit processes an analog signal. Also, in the solid-state image sensor, the pixel circuit generates an analog signal by photoelectric conversion, and outputs the analog signal to the logic circuit via a predetermined signal line. In the solid-state image sensor, the negative capacitance circuit is connected to the predetermined signal line.

Abstract: It makes it easier to reduce the line capacitance of vertical signal lines in a solid-state image sensor in which signals are output via the vertical signal lines. The solid-state image sensor is provided with a logic circuit, a pixel circuit, and a negative capacitance circuit. In the solid-state image sensor, the logic circuit processes an analog signal. Also, in the solid-state image sensor, the pixel circuit generates an analog signal by photoelectric conversion, and outputs the analog signal to the logic circuit via a predetermined signal line. In the solid-state image sensor, the negative capacitance circuit is connected to the predetermined signal line.

Abstract: A time-of-flight image sensor (TOF) for imaging with ambient light subtraction. In one embodiment, the TOF image sensor includes a pixel array including a plurality of pixel circuits, a control circuit, and a signal processing circuit. The signal processing circuit reads out a first data signal from respective floating diffusions during a first frame after a first reset of the respective floating diffusions and after a first integration of respective photoelectric conversion devices while a light generator is in a non-emission state, read out a second data signal from the respective floating diffusions after a second reset and after a second integration of the respective photoelectric conversion devices while the light generator is in an emission state, and generate a third data signal indicative of a light signal emitted by the light generator and reflected off an object.

Abstract: An image sensor and electronic apparatus comprise a pixel circuit configured to generate an analog signal; a vertical signal line configured to convey the analog signal from the pixel circuit; an analog amplifier circuit configured to receive the analog signal via the vertical signal line and generate an amplified signal; and a tail current boost circuit configured to modify an instantaneous gain bandwidth product of the analog amplifier circuit by temporarily modifying a tail current of the analog amplifier circuit.

Abstract: An image sensor and processing method therein comprises a pixel circuit configured to generate a pixel signal; a vertical signal line configured to convey the pixel signal; and a charge amplifier circuit configured to receive the pixel signal, the charge amplifier circuit being switched between a low bandwidth state and a high bandwidth state in response to a control signal.

Abstract: The present disclosure relates to an imaging device and an electronic device capable of restricting an occurrence of a sunspot phenomenon in a simple configuration. The imaging device includes a sample/hold part that samples and holds a reset voltage as a reset level voltage of a pixel signal and an AD conversion part that analog digital (AD) converts the pixel signal, in which the AD conversion part selects and outputs one of a first output signal as the AD converted pixel signal and a second output signal at a predetermined level on the basis of a comparison result between the reset voltage held by the sample/hold part and a predetermined reference voltage. The technology according to the present disclosure can be applied to a CMOS image sensor, for example.

Abstract: The present disclosure relates to an imaging device and an electronic device capable of restricting an occurrence of a sunspot phenomenon in a simple configuration. The imaging device includes: a sample/hold part configured to sample and hold a reset voltage as a reset level voltage of a pixel signal; and an AD conversion part configured to analog digital (AD) convert the pixel signal, in which the AD conversion part selects and outputs one of a first output signal as the AD converted pixel signal and a second output signal at a predetermined level on the basis of a comparison result between the reset voltage held by the sample/hold part and a predetermined reference voltage. The technology according to the present disclosure can be applied to a CMOS image sensor, for example.

Abstract: It makes it easier to reduce the line capacitance of vertical signal lines in a solid-state image sensor in which signals are output via the vertical signal lines. The solid-state image sensor is provided with a logic circuit, a pixel circuit, and a negative capacitance circuit. In the solid-state image sensor, the logic circuit processes an analog signal. Also, in the solid-state image sensor, the pixel circuit generates an analog signal by photoelectric conversion, and outputs the analog signal to the logic circuit via a predetermined signal line. In the solid-state image sensor, the negative capacitance circuit is connected to the predetermined signal line.

Abstract: An image sensor including a pixel circuit and an active reset circuit. The pixel circuit includes a light sensing element, a storage node selectively connected to the light sensing element, an output transistor configured to, during a readout operation, output a signal that is based on a potential of the charge storage node to an output line, and a selection transistor that controls the readout operation. The active reset circuit includes a first current path and a second current path, the first current path extending from a power supply node to the output line via the selection transistor and the output transistor, and the second current path extending from the power supply node to the output line via a first transistor and a second transistor. The active reset circuit is configured to, when the selection transistor and the first transistor are both ON, set a potential of the charge storage node based on a potential of a gate of the second transistor.

Abstract: A sample-and-hold-circuit includes an amplifier transistor, a resistor connected between a source terminal of the amplifier and a voltage, a first switch connected in parallel with the resistor, and a second switch connected between a gate terminal of the amplifier transistor and the voltage. When the first switch is closed and the second switch is open, the amplifier transistor is in an inversion mode; and when the first switch is open and the second switch is closed, the amplifier transistor is in an accumulation mode.

Abstract: The present technology is concerned with a solid-state imaging device, a method of driving a solid-state imaging device, and an electronic device which are capable of reducing power supply noise of a pixel signal with a single-ended circuit arrangement. The solid-state imaging device includes a pixel section including a plurality of unit pixels disposed for photoelectric transduction, a power supply noise detector detecting a noise component from a power supply used to energize the unit pixels and outputting a single-ended canceling signal including a canceling component for canceling the noise component, a sample and hold section configured to sample single-ended pixel signals output from the unit pixels and hold and output pixel signals representing the sampled pixel signals from which the noise component has been removed on the basis of the canceling signal, and an A/D converter performing A/D conversion on the pixel signals that have been held.

Abstract: A sample-and-hold circuit comprises a sampling capacitor; an amplifier transistor; and a noise reduction circuit including an integration capacitor and a feedback capacitor, the noise reduction circuit being configured to reduce noise via a four-phase operation including: an auto-zero phase in which the feedback capacitor is discharged, a feedback phase in which a gate voltage of the amplifier transistor is partially compensated through the feedback capacitor, an integration phase in which the integration capacitor is charged, and a feedforward phase in which the gate voltage of the amplifier transistor is fully compensated by a voltage on the integration capacitor through the feedback capacitor.

Abstract: An image sensor comprises a plurality of image pixel circuits arranged in an array; image processing circuitry including a sample-and-hold circuit configured to receive a first reference voltage and an analog-to-digital converter configured to receive a second reference voltage; and a reference adjustment circuit configured to selectively adjust the first reference voltage and/or the second reference voltage, thereby to match an operating range of the sample-and-hold circuit with an operating range of the analog-to-digital converter, based on a measurement signal.

Abstract: A sample-and-hold circuit comprises a sampling capacitor; an amplifier transistor; and a noise reduction circuit including an integration capacitor and a feedback capacitor, the noise reduction circuit being configured to reduce noise via a four-phase operation including: an auto-zero phase in which the feedback capacitor is discharged, a feedback phase in which a gate voltage of the amplifier transistor is partially compensated through the feedback capacitor, an integration phase in which the integration capacitor is charged, and a feedforward phase in which the gate voltage of the amplifier transistor is fully compensated by a voltage on the integration capacitor through the feedback capacitor.

Abstract: A signal processing device comprising at least one control unit arranged to receive at least one pack-insert instruction, decode the received at least one pack-insert instruction, and output at least one pack-insert control signal in accordance with the received pack-insert instruction. The signal processing device further comprising at least one pack-insert component arranged to receive at least a first data block to be inserted into a sequence of data blocks to be output to at least one destination register, receive a plurality of further data blocks to be packed within the sequence of data blocks to be output to the at least one destination register, arrange the at least first data block and the plurality of further data blocks into a sequence of data blocks based at least partly on the at least one pack-insert control signal, and output the sequence of data blocks.

Abstract: An image sensor including a pixel circuit and an active reset circuit. The pixel circuit includes a light sensing element, a storage node selectively connected to the light sensing element, an output transistor configured to, during a readout operation, output a signal that is based on a potential of the charge storage node to an output line, and a selection transistor that controls the readout operation. The active reset circuit includes a first current path and a second current path, the first current path extending from a power supply node to the output line via the selection transistor and the output transistor, and the second current path extending from the power supply node to the output line via a first transistor and a second transistor. The active reset circuit is configured to, when the selection transistor and the first transistor are both ON, set a potential of the charge storage node based on a potential of a gate of the second transistor.

Abstract: An image sensor including a pixel circuit and an active reset circuit. The pixel circuit includes a light sensing element, a storage node selectively connected to the light sensing element, an output transistor configured to, during a readout operation, output a signal that is based on a potential of the charge storage node to an output line, and a selection transistor that controls the readout operation. The active reset circuit includes a first current path and a second current path, the first current path extending from a power supply node to the output line via the selection transistor and the output transistor, and the second current path extending from the power supply node to the output line via a first transistor and a second transistor. The active reset circuit is configured to, when the selection transistor and the first transistor are both ON, set a potential of the charge storage node based on a potential of a gate of the second transistor.