Abstract: The subject technology is directed to an apparatus for managing data packets in a network. In an embodiment, the apparatus comprises a first memory configured to store a plurality of packets. The apparatus further comprises a queue manager configured to receive a plurality of packet descriptors and generate an aggregated packet descriptor based on the plurality of packet descriptors. The apparatus further comprises a traffic manager coupled to the queue manager. The traffic manager is configured to determine a transmission order for the plurality of packets based on the aggregated packet descriptor. A transmitter is coupled to the traffic manager and configured to transmit the plurality of packets based on the determined transmission order. This configuration enables efficient packet storage, aggregation, and transmission scheduling, optimizing overall network performance and resource utilization. There are other embodiments as well.

Abstract: An example traffic management system for a network device includes: a first memory storing queues of packets received by the network device; a second memory storing data of a scheduler for the queues that schedules transmission of the packets to a port of the network device; and an accelerator circuit including a third memory to store a data structure, the accelerator circuit coupled to the second memory and operable to: load, for a first iteration of a traverse operation in response to a command, a field of the data structure in the third memory with data from a first node of the scheduler; update, during the first iteration of the traverse operation, the field of the data structure in the third memory; and store, during the first iteration of the traverse operation, updated data from the field to the first node in the second memory.

Abstract: The present invention provides stable, liquid compositions comprising (a) a fungicidally effective amount of a compound of Formula I and (b) a liquid carrier. The present invention also provides mixtures and compositions comprising (a) a fungicidally effective amount of a compound of Formula I and (b) at least one adjuvant selected from the group consisting of: (i) polyalkylene oxide alkyl ether; (ii) siloxane polyalkyleneoxide copolymer; (iii) esters of fatty acid; (iv) vinylpyrrolidones and derivatives thereof; and (v) sugar-based surfactants. The present invention also provides methods of use of the mixtures and compositions disclosed herein and processes of preparing the mixtures and compositions disclosed herein.

Abstract: An example traffic management system for a network device includes: a first memory storing queues of packets received by the network device; a second memory storing data of a scheduler for the queues that schedules transmission of the packets to a port of the network device; and an accelerator circuit including a third memory to store a data structure, the accelerator circuit coupled to the second memory and operable to: load, for a first iteration of a traverse operation in response to a command, a field of the data structure in the third memory with data from a first node of the scheduler; update, during the first iteration of the traverse operation, the field of the data structure in the third memory; and store, during the first iteration of the traverse operation, updated data from the field to the first node in the second memory.

Abstract: The present invention provides stable, liquid compositions comprising (a) a fungicidally effective amount of a compound of Formula I and (b) a liquid carrier. The present invention also provides mixtures and compositions comprising (a) a fungicidally effective amount of a compound of Formula I and (b) at least one adjuvant selected from the group consisting of: (i) polyalkylene oxide alkyl ether: (ii) siloxane polyalkyleneoxide copolymer; (iii) esters of fatty acid; (iv) vinylpyrrolidones and derivatives thereof; and (v) sugar-based surfactants. The present invention also provides methods of use of the mixtures and compositions disclosed herein and processes of preparing the mixtures and compositions disclosed herein.

Abstract: The present invention provides a method of treating a locus against pest infestation using a compound of Formula I as described herein or an agriculturally acceptable salt thereof. The present invention also provides combinations and compositions comprising the compound of Formula I or an agriculturally acceptable salt thereof and uses thereof. The present invention also provides methods of extracting the compound of Formula I from a fungus.

Abstract: The present invention provides stable, liquid compositions comprising (a) a fungicidally effective amount of a compound of Formula I and (b) a liquid carrier. The present invention also provides mixtures and compositions comprising (a) a fungicidally effective amount of a compound of Formula I and (b) at least one adjuvant selected from the group consisting of: (i) polyalkylene oxide alkyl ether: (ii) siloxane polyalkyleneoxide copolymer; (iii) esters of fatty acid; (iv) vinylpyrrolidones and derivatives thereof; and (v) sugar-based surfactants. The present invention also provides methods of use of the mixtures and compositions disclosed herein and processes of preparing the mixtures and compositions disclosed herein.

Abstract: The present invention provides pesticidal compositions comprising an agriculturally acceptable carrier and at least one compound of Formula (A) or a salt thereof as described herein. The present invention also provides methods for the control or prevention of pest in a crop field, comprising applying the compound(s) of Formula (A) or pesticidal compositions thereof to the pest, a locus of the pest and/or an area in which pest infestation is to be prevented so as to thereby control or prevent pest in the crop field.

Abstract: A method and a device having a plurality of bit operations capability, the device includes: a first and a second registers and an instruction fetch circuit, and an arithmetic logic unit adapted to: calculate, during a first clock cycle, a position value representative of a position, within a first information vector, of a first bit of information that has a first value; and to multiply the position value by a multiplication factor to provide a first result and to alter the value of the first bit to a second value to provide an updated information vector, during the first clock cycle.

Abstract: The present invention relates to a composition comprising a combination of a morpholine fungicide; a phthalimide fungicide; and a phosphorus containing fungicide, wherein the composition has a synergistically enhanced activity.

Abstract: Compositions and methods employing combinations of synergistically effective amounts of folpet and epoxiconazole are provided.

Abstract: A method for transmitting data, the method includes scanning at least a first memory unit to retrieve data segments associated with multiple TDM channels, in response to a definition of multiple TDM time frames, each TDM time frame includes multiple time slots; sending the retrieved data segments to an array of line shifters; multiplexing data segments provided from the array of line shifters, in response to the definition, such as to provide in a parallel manner multiple data segments to multiple TDM lines; and transmitting a group of time division multiples data frames over a group of TDM lines.

Abstract: A method and a device for processing instructions based on register group size information includes a pipelined processor, an instruction memory unit and a register file, whereas the pipelined processor includes a write-back unit and an execution unit. The device is characterized by including a controller that is adapted to receive a first register group size information and a first register identification information that define a first group of source registers associated with a first instruction; and to determine an execution related operation of the first instruction in response to the first register group size information, the first register identification information, a second register group size information and a second register identification information. The second register group size information and the second register identification information define a second group of target registers associated with a second instruction.

Abstract: A device and method for processing information fragments, the method includes: receiving multiple information fragments from multiple communication paths; wherein the each information fragment is associated with a cyclic serial number indicating of a generation time of the information fragment; storing the multiple information fragments in multiple input queues, each input queue being associated with a communication path out of the multiple communication paths; determining whether at least one serial number associated with at least one valid information fragment positioned in a head of one of the multiple input queues is located within a pre-rollout serial number range; mapping, in response to the determination, serial numbers associated with each of the valid information fragment positioned in the heads of the multiple input queues to at least one serial number range that differs from the pre-rollout serial number range; and sending to an output queue information fragment metadata associated with a minimal v

Abstract: A method and a device having a plurality of bit operations capability, the device includes: a first and a second registers and an instruction fetch circuit, and an arithmetic logic unit adapted to: calculate, during a first clock cycle, a position value representative of a position, within a first information vector, of a first bit of information that has a first value; and to multiply the position value by a multiplication factor to provide a first result and to alter the value of the first bit to a second value to provide an updated information vector, during the first clock cycle.

Abstract: A device and method for processing information fragments, the method includes: receiving multiple information fragments from multiple communication paths; wherein the each information fragment is associated with a cyclic serial number indicating of a generation time of the information fragment; storing the multiple information fragments in multiple input queues, each input queue being associated with a communication path out of the multiple communication paths; determining whether at least one serial number associated with at least one valid information fragment positioned in a head of one of the multiple input queues is located within a pre-rollout serial number range; mapping, in response to the determination, serial numbers associated with each of the valid information fragment positioned in the heads of the multiple input queues to at least one serial number range that differs from the pre-rollout serial number range; and sending to an output queue information fragment metadata associated with a minimal v

Abstract: A method for transmitting data, the method includes scanning at least a first memory unit to retrieve data segments associated with multiple TDM channels, in response to a definition of multiple TDM time frames, each TDM time frame includes multiple time slots; sending the retrieved data segments to an array of line shifters; multiplexing data segments provided from the array of line shifters, in response to the definition, such as to provide in a parallel manner multiple data segments to multiple TDM lines; and transmitting a group of time division multiples data frames over a group of TDM lines

Abstract: A method and a device for processing instructions. The device includes a pipelined processor, an instruction memory unit and a register file, whereas the pipelined processor includes a write-back unit and an execution unit. The device is characterized by including a controller that is adapted to receive a first register group size information and a first register identification information that define a first group of source registers associated with a first instruction; and to determine an execution related operation of the first instruction in response to the first register group size information, the first register identification information, a second register group size information and a second register identification information. Whereas the second register group size information and the second register identification information define a second group of target registers associated with a second instruction.

Abstract: A method and a device. The device includes a single port memory unit that includes multiple memory regions, whereas each memory region is adapted to receive multiple data segments in parallel; whereas the single port memory unit receives a memory clock signal; characterized by including access logic adapted to receive multiple data segment write requests from multiple data sources; to write, during a first memory clock cycle, multiple data segments to a certain memory region in response to an availability of the certain memory region; to temporarily store rejected data segments; to write, during a second memory clock cycle, at least the rejected data segments, to another memory region.