Abstract: A column signal processing unit includes a current control circuit (110) and a feedback circuit (120). The current control circuit (110) is electrically connected between a data signal line (VSL) and a supply reference potential (GND). The feedback circuit (120) is configured to reduce a capacitive load of the data signal line (VSL). A feedback path (121) of the feedback circuit (120) includes a series connection of a feedback capacitor (122) and a delay element (123), wherein the delay element (123) is configured to increase a time delay in the feedback path (121).

Abstract: A pixel circuit (100) includes a photoelectric conversion circuit (110), an integration capacitor (Cint) and a supplementary circuit (120). The photoelectric conversion circuit (110) generates and outputs a photocurrent (Iphoto). The integration capacitor (Cint) includes a storage electrode (CintS) and a reference electrode (CintR), wherein the reference electrode (CintR) is connected to a first supply potential (VSUP1), and wherein the integration capacitor (Cint) is configured to integrate the photocurrent on the storage electrode (CintS) in an integration period (Tint). The supplementary circuit (120) pre-charges a working node (WN) between the photoelectric conversion circuit (110) and the storage electrode (CintS) to a pre-charge potential (Vpre) that differs from the first supply potential (VSUP1).