Patents by Inventor Nobert Rehm
Nobert Rehm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7102908Abstract: The present invention includes a ferro fuse cell comprising a ferroelectric storage capacitor electrically connected to a plate on one side and to a sense amplifier on the other side. A ferroelectric measurement capacitor is electrically connected between the ferroelectric storage capacitor and the sense amplifier.Type: GrantFiled: August 29, 2003Date of Patent: September 5, 2006Assignee: Infineon Technologies AGInventors: Roehr Thomas, Hans-Oliver Joachim, Nobert Rehm
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Patent number: 7092274Abstract: A ferroelectric memory device includes a memory cell array having memory cells arranged in a matrix form. Each of the memory cells includes a cell transistor and a ferroelectric capacitor. It further includes a first dummy bit line arranged outside a bit line arranged on an end portion of the memory cell array and separated from the bit line arranged on the end portion of the memory cell array with an interval which is the same as a pitch between the bit lines in the memory cell array and having the same width as the bit line, and a first dummy memory cell connected to the first dummy bit line and having the same structure as the memory cell.Type: GrantFiled: October 14, 2004Date of Patent: August 15, 2006Assignees: Kabushiki Kaisha Toshiba, Infineon Technologies, AGInventors: Katsuhiko Hoya, Daisaburo Takashima, Nobert Rehm
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Patent number: 6876590Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data and connecting a cell plate line to a first bit line through a first select transistor. The first select transistor activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines. A third transistor transfers charge between the first and second bit lines third to reduce the differential read signal.Type: GrantFiled: November 20, 2002Date of Patent: April 5, 2005Assignee: Infineon Technologies, AGInventors: Hans-Oliver Joachim, Michael Jacob, Nobert Rehm
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Publication number: 20050047188Abstract: A ferroelectric memory device includes a memory cell array having memory cells arranged in a matrix form. Each of the memory cells includes a cell transistor and a ferroelectric capacitor. It further includes a first dummy bit line arranged outside a bit line arranged on an end portion of the memory cell array and separated from the bit line arranged on the end portion of the memory cell array with an interval which is the same as a pitch between the bit lines in the memory cell array and having the same width as the bit line, and a first dummy memory cell connected to the first dummy bit line and having the same structure as the memory cell.Type: ApplicationFiled: October 14, 2004Publication date: March 3, 2005Inventors: Katsuhiko Hoya, Daisaburo Takashima, Nobert Rehm
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Publication number: 20050050261Abstract: A data storage device comprises a controller, a FeRAM memory unit, and a flash memory unit having a much higher data storage capacity than the FeRAM memory unit. Initially, when data is received by the data storage device, the controller stores it in the FeRAM memory unit. This can be done very quickly, since FeRAM devices have a high write rate. Subsequently, the controller transfers the data to the flash memory unit. Thus, the data storage device combines the high storage rate ability of FeRAM devices and the high storage capacity of flash memory devices.Type: ApplicationFiled: August 27, 2003Publication date: March 3, 2005Inventors: Thomas Roehr, Michael Jacob, Nobert Rehm, Hans-Oliver Joachim
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Publication number: 20040252542Abstract: A ferroelectric memory device includes a memory cell array having memory cells arranged in a matrix form. Each of the memory cells includes a cell transistor and a ferroelectric capacitor. It further includes a first dummy bit line arranged outside a bit line arranged on an end portion of the memory cell array and separated from the bit line arranged on the end portion of the memory cell array with an interval which is the same as a pitch between the bit lines in the memory cell array and having the same width as the bit line, and a first dummy memory cell connected to the first dummy bit line and having the same structure as the memory cell.Type: ApplicationFiled: June 16, 2003Publication date: December 16, 2004Inventors: Katsuhiko Hoya, Daisaburo Takashima, Nobert Rehm
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Patent number: 6822891Abstract: A ferroelectric memory device includes a memory cell array having memory cells arranged in a matrix form. Each of the memory cells includes a cell transistor and a ferroelectric capacitor. It further includes a first dummy bit line arranged outside a bit line arranged on an end portion of the memory cell array and separated from the bit line arranged on the end portion of the memory cell array with an interval which is the same as a pitch between the bit lines in the memory cell array and having the same width as the bit line, and a first dummy memory cell connected to the first dummy bit line and having the same structure as the memory cell.Type: GrantFiled: June 16, 2003Date of Patent: November 23, 2004Assignees: Kabushiki Kaisha Toshiba, Infineon Technologies, AGInventors: Katsuhiko Hoya, Daisaburo Takashima, Nobert Rehm
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Publication number: 20040095820Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account A semiconductor memory test mode configuration includes a first capacitor for storing digital data connecting a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines.Type: ApplicationFiled: November 20, 2002Publication date: May 20, 2004Inventors: Michael Jacob, Joerg Wohlfahrt, Thomas Roehr, Nobert Rehm
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Publication number: 20040095821Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data and connecting a cell plate line to a first bit line through a first select transistor. The first select transistor activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines. A third transistor transfers charge between the first and second bit lines third to reduce the differential read signal.Type: ApplicationFiled: November 20, 2002Publication date: May 20, 2004Inventors: Hans-Oliver Joachim, Michael Jacob, Nobert Rehm
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Patent number: 6731554Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data connecting a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line.Type: GrantFiled: November 20, 2002Date of Patent: May 4, 2004Assignee: Infineon Technologies AGInventors: Michael Jacob, Joerg Wohlfahrt, Thomas Roehr, Nobert Rehm