Patents by Inventor Noboru Akiyama
Noboru Akiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10040700Abstract: A light-shielding strip, for preventing a sealing member from deterioration due to ultraviolet rays, is made of a ultraviolet-shielding material having a resilient plate shape, and comprises: a main light-shielding portion having a length according to at least a circumferential length of an inner periphery of a lamp-protective tube; and first and second overlap portions extending from respective ones of both ends of the main light-shielding portion in a longitudinal direction with each forming a non-parallel convergence shape. The light-shielding strip, rolled in the longitudinal direction, is disposed in the lamp-protective tube to closely fit to the inner periphery of the lamp-protective tube and positioned to oppose to the sealing member. Repulsive force against bending force around an end portion of the light-shielding strip can be dispersed due to the non-parallel convergence shape of the overlap portions, so that a possible-raised portion around the end portion can be suppressed.Type: GrantFiled: March 9, 2016Date of Patent: August 7, 2018Assignee: PHOTOSCIENCE JAPAN CORPORATIONInventors: Noboru Akiyama, Yuji Yamakoshi
-
Patent number: 9977090Abstract: Disclosed is a method for manufacturing an electrochemical cell, wherein an insulation failure product can be accurately rejected, and an electrochemical cell can be used again after the insulation failure inspection. In the method for manufacturing the electrochemical cell (1), which is configured by hermetically housing an electrochemical cell main body (20) such that the leading end of a metal terminal (21) protrudes to the outside of the outer housing (10), an impulse voltage is applied between the metal terminal (21) and a metal foil layer (12), the waveform of the voltage applied to the capacitance between the metal terminal (21) and the metal foil layer (12) is measured, and the insulation failure inspection step is performed.Type: GrantFiled: June 1, 2015Date of Patent: May 22, 2018Assignee: DAI NIPPON PRINTING CO., LTD.Inventors: Takanori Yamashita, Hirohisa Akita, Noboru Akiyama, Masataka Okushita
-
Publication number: 20180072590Abstract: A light-shielding strip, for preventing a sealing member from deterioration due to ultraviolet rays, is made of a ultraviolet-shielding material having a resilient plate shape, and comprises: a main light-shielding portion having a length according to at least a circumferential length of an inner periphery of a lamp-protective tube; and first and second overlap portions extending from respective ones of both ends of the main light-shielding portion in a longitudinal direction with each forming a non-parallel convergence shape. The light-shielding strip, rolled in the longitudinal direction, is disposed in the lamp-protective tube to closely fit to the inner periphery of the lamp-protective tube and positioned to oppose to the sealing member. Repulsive force against bending force around an end portion of the light-shielding strip can be dispersed due to the non-parallel convergence shape of the overlap portions, so that a possible-raised portion around the end portion can be suppressed.Type: ApplicationFiled: March 9, 2016Publication date: March 15, 2018Inventors: Noboru AKIYAMA, Yuji YAMAKOSHI
-
Publication number: 20160109896Abstract: In order to reduce parasitic inductance of a main circuit in a power supply circuit, a non-insulated DC-DC converter is provided having a circuit in which a power MOS·FET for a high-side switch and a power MOS·FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS·FET for the high-side switch is formed by a p channel vertical MOS·FET, and the power MOS·FET for the low-side switch is formed by an n channel vertical MOS·FET. Thus, a semiconductor chip formed with the power MOS·FET for the high-side switch and a semiconductor chip formed with the power MOS·FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.Type: ApplicationFiled: December 27, 2012Publication date: April 21, 2016Inventors: Masaki SHIRAISHI, Noboru AKIYAMA, Tomoaki UNO, Nobuyoshi MATSUURA
-
Publication number: 20150260797Abstract: Disclosed is a method for manufacturing an electrochemical cell, wherein an insulation failure product can be accurately rejected, and an electrochemical cell can be used again after the insulation failure inspection. In the method for manufacturing the electrochemical cell (1), which is configured by hermetically housing an electrochemical cell main body (20) such that the leading end of a metal terminal (21) protrudes to the outside of the outer housing (10), an impulse voltage is applied between the metal terminal (21) and a metal foil layer (12), the waveform of the voltage applied to the capacitance between the metal terminal (21) and the metal foil layer (12) is measured, and the insulation failure inspection step is performed.Type: ApplicationFiled: June 1, 2015Publication date: September 17, 2015Applicant: DAI NIPPON PRINTING CO., LTD.Inventors: Takanori YAMASHITA, Hirohisa AKITA, Noboru AKIYAMA, Masataka OKUSHITA
-
Patent number: 9076601Abstract: A method for manufacturing an electrochemical cell includes housing a main cell body in an outer packaging body of packaging material formed by laminating a metal foil layer and a heat-sealable resin layer, provided the tip ends of a first metal terminal and a second metal terminal are protruding outside the outer packaging body, heat-sealing a peripheral edge portion of the outer packaging body so the outer packaging body has the first and second terminals protruding; applying a voltage between the first terminal and the foil layer or between the second terminal and the foil layer; and inspecting for insulation failure from a short circuit between the first or second terminal and the foil layer or from a crack in the heat-sealable resin layer, based on a variation of a voltage held between the one of the metal terminals and the metal foil layer after halting the voltage.Type: GrantFiled: September 29, 2010Date of Patent: July 7, 2015Assignee: DAI NIPPON PRINTING CO., LTD.Inventors: Takanori Yamashita, Hirohisa Akita, Noboru Akiyama, Masataka Okushita
-
Patent number: 8901838Abstract: The semiconductor device is included in the LED driving circuit (current regulator) of driving the LED array (with series-connected number m×parallel-connected number n), and is formed of a plurality (n pieces) of LED driving devices of controlling a current (constant-current driving) flowing in each string. A vertical semiconductor device, for example, a vertical MOSFET is used as the LED driving device. Both of a main device functioning as a constant-current driving device and a subsidiary device functioning as a circuit-breaking switch during dimming are formed inside a chip of the device, which are formed of the vertical semiconductor devices. In a first surface of the device, each source region of the main device and the subsidiary device is formed so as to be insulated from each other through an isolation region.Type: GrantFiled: July 27, 2012Date of Patent: December 2, 2014Assignee: Renesas Electronics CorporationInventors: Noboru Akiyama, Takayuki Hashimoto, Takashi Hirao, Nobuyoshi Matsuura, Hideo Ishii
-
Patent number: 8664716Abstract: In a lateral-type power MOSFET, high breakdown voltage is achieved with suppressing to increase a cell pitch, and a feedback capacity and an ON resistance are decreased. An n? type silicon region having a high resistance to be a region of maintaining a breakdown voltage is vertically provided with respect to a main surface of an n+ type silicon substrate, and the n? type silicon region having the high resistance is connected to the n+ type silicon substrate. Also, a conductive substance is filled through an insulating substance inside a trench formed to reach the n+ type silicon substrate from the main surface of the n+ type silicon substrate so as to contact with the n? type silicon region having the high resistance, and the conductive substance is electrically connected to a source electrode.Type: GrantFiled: June 18, 2010Date of Patent: March 4, 2014Assignee: Renesas Electronics CorporationInventors: Takayuki Hashimoto, Takashi Hirao, Noboru Akiyama
-
Patent number: 8638577Abstract: In a non-isolated DC/DC converter, a reference potential for a low-side pre-driver which drives a gate of a low-side MOSFET is applied from a portion except for a main circuit passing through a high-side MOSFET and the low-side MOSFET so that a parasitic inductance between a source of the low-side MOSFET and the pre-driver is increased without increasing the sum of parasitic inductances in the main circuit and negative potential driving of the gate of the low-side MOSFET can be performed and a self turn-on phenomenon can be prevented without adding any member and changing drive system.Type: GrantFiled: September 13, 2011Date of Patent: January 28, 2014Assignee: Renesas Electronics CorporationInventors: Masaki Shiraishi, Takayuki Hashimoto, Noboru Akiyama
-
Publication number: 20130106388Abstract: In order to reduce parasitic inductance of a main circuit in a power supply circuit, a non-insulated DC-DC converter is provided having a circuit in which a power MOS·FET for a high-side switch and a power MOS·FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS·FET for the high-side switch is formed by a p channel vertical MOS·FET, and the power MOS·FET for the low-side switch is formed by an n channel vertical MOS·FET. Thus, a semiconductor chip formed with the power MOS·FET for the high-side switch and a semiconductor chip formed with the power MOS·FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.Type: ApplicationFiled: December 27, 2012Publication date: May 2, 2013Inventors: Masaki SHIRAISHI, Noboru AKIYAMA, Tomoaki UNO, Nobuyoshi MATSUURA
-
Patent number: 8345458Abstract: In order to reduce parasitic inductance of a main circuit in a power supply circuit, a non-insulated DC-DC converter is provided having a circuit in which a power MOS•FET for a high-side switch and a power MOS•FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS•FET for the high-side switch is formed by a p channel vertical MOS•FET, and the power MOS•FET for the low-side switch is formed by an n channel vertical MOS•FET. Thus, a semiconductor chip formed with the power MOS•FET for the high-side switch and a semiconductor chip formed with the power MOS•FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.Type: GrantFiled: November 10, 2011Date of Patent: January 1, 2013Assignee: Renesas Electronics CorporationInventors: Masaki Shiraishi, Noboru Akiyama, Tomoaki Uno, Nobuyoshi Matsuura
-
Patent number: 8319289Abstract: A technique for suppressing lowering of withstand voltage and lowering of breakdown resistance and reducing a feedback capacitance of a power MISFET is provided. A lateral power MISFET that comprises a trench region whose insulating layer is formed shallower than an HV-Nwell layer is provided in the HV-Nwell layer (drift region) formed on a main surface of a semiconductor substrate in a direction from the main surface to the inside. The lateral power MISFET has an arrangement on a plane of the main surface including a source layer (source region) and a drain layer (drain region) arranged at opposite sides to each other across a gate electrode (first conducting layer), and a dummy gate electrode (second conducting layer) that is different from the gate electrode is arranged between the gate electrode and the drain layer.Type: GrantFiled: December 27, 2007Date of Patent: November 27, 2012Assignee: Renesas Electronics CorporationInventors: Masaki Shiraishi, Noboru Akiyama, Takayuki Hashimoto
-
Publication number: 20120287097Abstract: The semiconductor device is included in the LED driving circuit (current regulator) of driving the LED array (with series-connected number m×parallel-connected number n), and is formed of a plurality (n pieces) of LED driving devices of controlling a current (constant-current driving) flowing in each string. A vertical semiconductor device, for example, a vertical MOSFET is used as the LED driving device. Both of a main device functioning as a constant-current driving device and a subsidiary device functioning as a circuit-breaking switch during dimming are formed inside a chip of the device, which are formed of the vertical semiconductor devices. In a first surface of the device, each source region of the main device and the subsidiary device is formed so as to be insulated from each other through an isolation region.Type: ApplicationFiled: July 27, 2012Publication date: November 15, 2012Applicant: Renesas Electronics CorporationInventors: Noboru AKIYAMA, Takayuki HASHIMOTO, Takashi HIRAO, Nobuyoshi MATSUURA, Hideo ISHII
-
Patent number: 8258711Abstract: The semiconductor device is included in the LED driving circuit (current regulator) of driving the LED array (with series-connected number m×parallel-connected number n), and is formed of a plurality (n pieces) of LED driving devices of controlling a current (constant-current driving) flowing in each string. A vertical semiconductor device, for example, a vertical MOSFET is used as the LED driving device. Both of a main device functioning as a constant-current driving device and a subsidiary device functioning as a circuit-breaking switch during dimming are formed inside a chip of the device, which are formed of the vertical semiconductor devices. In a first surface of the device, each source region of the main device and the subsidiary device is formed so as to be insulated from each other through an isolation region.Type: GrantFiled: May 13, 2010Date of Patent: September 4, 2012Assignee: Renesas Electronics CorporationInventors: Noboru Akiyama, Takayuki Hashimoto, Takashi Hirao, Nobuyoshi Matsuura, Hideo Ishii
-
Publication number: 20120186071Abstract: Disclosed is a method for manufacturing an electrochemical cell, wherein an insulation failure product can be accurately rejected, and an electrochemical cell can be used again after the insulation failure inspection. In the method for manufacturing the electrochemical cell (1), which is configured by hermetically housing an electrochemical cell main body (20) such that the leading end of a metal terminal (21) protrudes to the outside of the outer housing (10), an impulse voltage is applied between the metal terminal (21) and a metal foil layer (12), the waveform of the voltage applied to the capacitance between the metal terminal (21) and the metal foil layer (12) is measured, and the insulation failure inspection step is performed.Type: ApplicationFiled: September 29, 2010Publication date: July 26, 2012Applicant: DAI NIPPON PRINTING CO., LTD.Inventors: Takanori Yamashita, Hirohisa Akita, Noboru Akiyama, Masataka Okushita
-
Patent number: 8203380Abstract: In a semiconductor device, a high-side driver is arranged in a region closer to a periphery of a semiconductor substrate than a high-side switch, and a low-side driver is arranged in a region closer to the periphery of the semiconductor substrate than the low-side switch. By this means, a path from a positive terminal of an input capacitor to a negative terminal of the input capacitor via the high-side switch and the low-side switch is short, a path from a positive terminal of a drive capacitor to a negative terminal of the drive capacitor via the low-side driver is short, and a path from a positive terminal of a boot strap capacitor to a negative terminal of the boot strap capacitor via the high-side driver is short, and therefore, the parasitic inductance can be reduced, and the conversion efficiency can be improved.Type: GrantFiled: June 12, 2009Date of Patent: June 19, 2012Assignee: Renesas Electronics CorporationInventors: Takayuki Hashimoto, Takashi Hirao, Noboru Akiyama
-
Publication number: 20120049290Abstract: In order to reduce parasitic inductance of a main circuit in a power supply circuit, a non-insulated DC-DC converter is provided having a circuit in which a power MOS•FET for a high-side switch and a power MOS•FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS•FET for the high-side switch is formed by a p channel vertical MOS•FET, and the power MOS•FET for the low-side switch is formed by an n channel vertical MOS•FET. Thus, a semiconductor chip formed with the power MOS•FET for the high-side switch and a semiconductor chip formed with the power MOS•FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.Type: ApplicationFiled: November 10, 2011Publication date: March 1, 2012Inventors: Masaki SHIRAISHI, Noboru AKIYAMA, Tomoaki UNO, Nobuyoshi MATSUURA
-
Patent number: 8125206Abstract: A power-supply control IC is included in a switching power supply which drives to turn on and off a semiconductor switching device connected to a DC power supply in series to supply a predetermined constant voltage to an external load, and is a semiconductor device including a semiconductor circuit which controls on and off of the semiconductor switching device. When a current flowing through the load is abruptly increased to cause an error voltage to exceed a predetermined first threshold voltage after the end of a PWM on-pulse generated in synchronization with a switching cycle, a second PWM on-pulse is generated within the same switching cycle. Furthermore, in a plurality of switching cycles after the switching cycle in which the second PWM on-pulse is generated, the first threshold voltage for comparison with the error voltage is switched to a second threshold voltage higher than the first threshold voltage.Type: GrantFiled: June 20, 2008Date of Patent: February 28, 2012Assignee: Renesas Electronics CorporationInventors: Noboru Akiyama, Takayuki Hashimoto, Takashi Hirao, Koji Tateno
-
Patent number: 8120345Abstract: A semiconductor device for control applied to a constant-voltage power supply device includes a digital-analog converter circuit which outputs a reference voltage corresponding to a value of a first register with taking an output voltage of a reference voltage source as a criterial reference voltage, and generates a control signal for driving a power semiconductor device based on an output voltage of an error amplifier which differentially amplifies a feedback voltage obtained by resistive-dividing on an output voltage of the constant-voltage power supply device and the reference voltage. An analog-digital converter circuit which converts the feedback voltage to a digital value with taking the output voltage of the constant-voltage power supply device as a reference voltage is provided, and based on the output, a value of a first register is corrected so as to offset an effect of an error in voltage dividing ratio of a voltage dividing resistor circuit.Type: GrantFiled: February 19, 2009Date of Patent: February 21, 2012Assignee: Renesas Electronics CorporationInventors: Noboru Akiyama, Takayuki Hashimoto, Takashi Hirao, Koji Tateno, Takuya Ishigaki
-
Publication number: 20120001609Abstract: In a non-isolated DC/DC converter, a reference potential for a low-side pre-driver which drives a gate of a low-side MOSFET is applied from a portion except for a main circuit passing through a high-side MOSFET and the low-side MOSFET so that a parasitic inductance between a source of the low-side MOSFET and the pre-driver is increased without increasing the sum of parasitic inductances in the main circuit and negative potential driving of the gate of the low-side MOSFET can be performed and a self turn-on phenomenon can be prevented without adding any member and changing drive system.Type: ApplicationFiled: September 13, 2011Publication date: January 5, 2012Inventors: Masaki SHIRAISHI, Takayuki Hashimoto, Noboru Akiyama