Abstract: A vehicle air conditioning duct structure includes: a front defroster nozzle which is provided in a vehicle front part, extends in a vehicle width direction, and is formed such that one end portion is connected to an air conditioning device disposed on a rear surface side of an instrument panel and the other end portion is disposed inside a front pillar and is provided with a front side air outlet opening toward a windshield glass; and a side defroster nozzle which is branched from an upstream side of the front side air outlet of the front defroster nozzle and of which a tip portion is provided with a side air outlet opening toward a front side glass.

Abstract: A general-purpose OS (operating system) is used as a host OS and a real-time OS operating as one or more tasks on the host OS is used as a guest OS. An interrupt handler and a task on the host OS and an interrupt handler and a task on the guest OS issue APIs (application program interfaces) for requesting task state change to a start, stop or like state. An API processor is provided in each OS and outputs an instruction for task state change. An instruction storage for storing instructions output from an API processor of the guest OS in order and outputting the instructions is provided. When interrupt handlers are not in execution, an instruction synchronization timing controller preferentially selects from instructions output from the API processor of the host OS and from the instruction storage the latter and outputs the selected instruction to a scheduler.

Abstract: A semiconductor device has a processor, a first memory unit accessed by the processor, a plurality of page memory units obtained by partitioning a second memory unit which is accessible by the processor at a speed higher than the speed at which the first memory unit is accessible such that each of the page memory units has a storage capacity larger than the memory capacity of a line composing a cache memory, a tag adding, to each of the page memory units, tag information indicative of an address value in the first memory unit and priority information indicative of a replacement priority, a tag comparator for comparing, upon receipt of an access request from the processor, the address value in the first memory unit with the tag information held by the tag, and a replacement control unit for replacing the respective contents of the page memory units.

Abstract: An interrupt control apparatus comprising an interrupt vector register for holding address information corresponding to interrupt resources of a first type which are managed by an operating system and interrupt resources of a second type which are not managed by the operating system. Regarding an interrupt generated by an interrupt resource of the first type, the interrupt control apparatus in the present invention launches a common interrupt entry function which is subject to a scheduling process common to the interrupt resources of the first type, based on the address information of the interrupt vector register. At the same time, with regard to an interrupt generated by an interrupt resource of the second type, the interrupt control apparatus in the present invention launches an extended interrupt entry function which is not subject to the aforementioned scheduling process, based on the address information held in the interrupt vector register.

Abstract: A general-purpose OS (operating system) is used as a host OS and a real-time OS operating as one or more tasks on the host OS is used as a guest OS. An interrupt handler and a task on the host OS and an interrupt handler and a task on the guest OS issue APIs (application program interfaces) for requesting task state change to a start, stop or like state. An API processor is provided in each OS and outputs an instruction for task state change. An instruction storage for storing instructions output from an API processor of the guest OS in order and outputting the instructions is provided. When each of the interrupt handlers is not in execution, an instruction synchronization timing controller preferentially selects from instructions output from the API processor of the host OS and from the instruction storage the latter and outputs the selected instruction to a scheduler.

Abstract: The interrupt control apparatus in the present invention includes an interrupt vector register for holding address information corresponding respectively to interrupt resources of first type which are managed by an operating system and interrupt resources of second type which are not managed by the operating system, from among the interrupt resources. With regard to an interrupt generated by an interrupt resource of first type managed by the operating system, the interrupt control apparatus in the present invention launches a common interrupt entry function which is subject to a scheduling process common to the interrupt resources of first type, based on the address information of the interrupt vector register.

Abstract: A semiconductor device has a processor, a first memory unit accessed by the processor, a plurality of page memory units obtained by partitioning a second memory unit which is accessible by the processor at a speed higher than the speed at which the first memory unit is accessible such that each of the page memory units has a storage capacity larger than the memory capacity of a line composing a cache memory, a tag adding, to each of the page memory units, tag information indicative of an address value in the first memory unit and priority information indicative of a replacement priority, a tag comparator for comparing, upon receipt of an access request from the processor, the address value in the first memory unit with the tag information held by the tag, and a replacement control unit for replacing the respective contents of the page memory units.

Abstract: A method of visualizing the results of performance monitoring and analysis for a parallel computing system in which a plurality of processors execute a parallel processing program composed of a plurality of routines. First, information on the execution time of each routine is collected in a realtime manner while the program is concurrently executed by the plurality of processors. Second, a maximum, average, and minimum values of the execution time of each routine are calculated, based on the information collected for the plurality of processors. Third, the collected information is summarized as an execution profile and displayed in graphical form by using bar graphs, pie graphs, or radar charts. For each procedure or program loop, the present method clarifies the percentages of net user program execution, communication, synchronization, and other parallelization overheads, as well as indicating their deviations.