Abstract: There is provided a structure manufacturing method, including: preparing an etching target at least whose top surface comprises group III nitride crystal, and an alkaline or acidic etching liquid containing peroxodisulfate ion as an oxidizing agent that receives electrons; irradiating the top surface of the etching target with light while rotating the etching target, with the top surface of the etching target immersed in the etching liquid heated to generate sulfate ion radicals.

Abstract: There is provided a structure manufacturing method, including: preparing a wafer at least whose surface comprises Group III nitride crystal in a state of being immersed in an etching solution containing peroxodisulfate ions; and irradiating the surface of the wafer with light through the etching solution; wherein the group III nitride crystal has a composition in which a wavelength corresponding to a band gap is 310 nm or more, and during irradiation of the light, the surface of the wafer is irradiated with a first light having a wavelength of 200 nm or more and less than 310 nm under a first irradiation condition, and is irradiated with a second light having a wavelength of 310 nm or more and less than a wavelength corresponding to the band gap under a second irradiation condition controlled independently of the first irradiation condition.

Abstract: A production apparatus for producing a structural body includes: a holding mechanism that holds a processing target in contact with an etching solution, the processing target including an etch region that is made of a Group III nitride, and on which photoelectrochemical etching is to be performed; a light emitting device that irradiates the processing target with first light for performing the photoelectrochemical etching; a light emitting device that irradiates the processing target with second light that has a wavelength longer than that of the first light; and a measurement device that measures reflected light resulting from the second light being reflected off a surface of the etch region.

Abstract: There is provided a semiconductor device, including: a substrate; a group III nitride layer on the substrate, the group III nitride layer containing group III nitride; and a recess on the group III nitride layer, the group III nitride layer including: a channel layer, and a barrier layer on the channel layer, thereby forming a two-dimensional electron gas in the channel layer, the barrier layer including: a first layer containing aluminum gallium nitride, and a second layer on the first layer, the second layer containing aluminum gallium nitride added with an n-type impurity, wherein the recess is formed by removing all or a part of a thickness of the second layer, and at least a part of a thickness of the first layer is arranged below the recess.

Abstract: A method for manufacturing a structure, including photoelectrochemically etching an etching object, the photoelectrochemical etching of the etching object including: injecting an alkaline or acidic etching solution containing an oxidizing agent that receives electrons, into a rotatably held container in which an etching object at least whose surface is composed of group III nitride is held, and immersing the surface in the etching solution; irradiating the surface of the etching object held in the container with light in a stationary state of the etching object and the etching solution; and rotating the container to scatter the etching solution toward an outer peripheral side, thereby discharging the etching solution from the container, after the surface is irradiated with the light.

Abstract: There is provided a method for manufacturing a structure, including: forming a recess portion by performing a first etching to a surface of a member composed of Group III nitride; and flattening a bottom of the recess portion by performing a second etching to the bottom, wherein in forming the recess portion, a flat portion and a protruding portion are formed on the bottom of the recess portion, the protruding portion being raised with respect to the flat portion because it is less likely to be etched by the first etching than the flat portion, and in flattening the bottom, by etching the protruding portion by the second etching, the protruding portion is lowered.

Abstract: There is provided a method for manufacturing a structure, including: applying a first etching to a surface of a member, at least the surface being composed of Group III nitride; and applying a second etching to the surface to which the first etching has been applied, wherein in applying the first etching, a flat portion and a protruding portion are formed, the flat portion being newly appeared on the surface by etching, and the protruding portion being raised with respect to the flat portion, which is caused by being less likely to be etched than the flat portion, and in applying the second etching, the protruding portion is lowered by etching the protruding portion.

Abstract: There is provided a structure manufacturing method, including: preparing a wafer at least whose surface comprises Group III nitride crystal in a state of being immersed in an etching solution containing peroxodisulfate ions; and irradiating the surface of the wafer with light through the etching solution; wherein the group III nitride crystal has a composition in which a wavelength corresponding to a band gap is 310 nm or more, and during irradiation of the light, the surface of the wafer is irradiated with a first light having a wavelength of 200 nm or more and less than 310 nm under a first irradiation condition, and is irradiated with a second light having a wavelength of 310 nm or more and less than a wavelength corresponding to the band gap under a second irradiation condition controlled independently of the first irradiation condition.

Abstract: A structure manufacturing method including: preparing a treatment object that includes an etching target having a surface to be etched comprising a conductive group III nitride and a region to be etched, a conductive member in contact with at least a portion of a surface of a conductive region of the etching target that is electrically connected to the region to be etched, and a mask formed on the surface to be etched and comprising a non-conductive material; and etching the group III nitride by immersing the treatment object in an alkaline or acidic etching solution containing peroxodisulfate ions as an oxidizing agent that accepts electrons, and irradiating the surface to be etched with light through the etching solution, wherein an edge that defines the region to be etched is constituted by an edge of the mask without including an edge of the conductive member.

Abstract: There is provided a structure manufacturing method, including: preparing an etching target with at least one surface comprising group III nitride; then in a state where the etching target is immersed in an etching solution containing peroxodisulfate ions; irradiating the surface of the etching target with light through the etching solution, and generating sulfate ion radicals from the peroxodisulfate ions and generating holes in the group III nitride, thereby etching the group III nitride, wherein in the etching of the group III nitride, the etching solution remains acidic during a period for etching the group III nitride by making the etching solution acidic at a start of etching the group III nitride, and the etching is performed, with a resist mask formed on the surface.

Abstract: There is provided a structure manufacturing method, including: preparing a wafer at least whose surface comprises Group III nitride crystal in a state of being immersed in an etching solution containing peroxodisulfate ions; and irradiating the surface of the wafer with light through the etching solution; wherein the group III nitride crystal has a composition in which a wavelength corresponding to a band gap is 310 nm or more, and during irradiation of the light, the surface of the wafer is irradiated with a first light having a wavelength of 200 nm or more and less than 310 nm under a first irradiation condition, and is irradiated with a second light having a wavelength of 310 nm or more and less than a wavelength corresponding to the band gap under a second irradiation condition controlled independently of the first irradiation condition.

Abstract: There is provided a method for manufacturing a nitride-based high electron mobility transistor, including: providing a conductive member on a nitride semiconductor crystal substrate, outside an element region in a plan view; forming a mask on the substrate, the mask having an opening in at least one of a source recess etching region and a drain recess etching region; performing photoelectrochemical etching by irradiating the substrate with light to form at least one of a source recess and a drain recess, in a state where the substrate on which the conductive member is provided and the mask is formed is in contact with an etching solution containing an oxidizing agent that receives electrons; and forming an element separation structure of the high electron mobility transistor.

Abstract: There is provided a structure manufacturing method, including: preparing a wafer at least whose surface comprises Group III nitride crystal in a state of being immersed in an etching solution containing peroxodisulfate ions; and irradiating the surface of the wafer with light through the etching solution; wherein the group III nitride crystal has a composition in which a wavelength corresponding to a band gap is 310 nm or more, and during irradiation of the light, the surface of the wafer is irradiated with a first light having a wavelength of 200 nm or more and less than 310 nm under a first irradiation condition, and is irradiated with a second light having a wavelength of 310 nm or more and less than a wavelength corresponding to the band gap under a second irradiation condition controlled independently of the first irradiation condition.

Abstract: A semiconductor substrate in includes a buffer layer and a first crystalline layer. A bandgap of the first crystalline layer is smaller than a bandgap of a second layer. When a semiconductor wafer is formed as a transistor wafer, a channel of a transistor is formed at or near an interface between the first crystalline layer and the second layer. With a first electrode and a second electrode provided and a third electrode provided, when space charge redistribution, for emitting electrons and holes from a bandgap of a crystal positioned in the spatial region, is achieved by applying negative voltage to the third electrode or by applying positive voltage to the second electrode with the first electrode serving as a reference, an electron emission speed in the space charge redistribution is higher than a hole emission speed.

Abstract: There is provided a structure manufacturing method, including: preparing an etching target with at least one surface comprising group III nitride; then in a state where the etching target is immersed in an etching solution containing peroxodisulfate ions, irradiating the surface of the etching target with light through the etching solution, and generating sulfate ion radicals from the peroxodisulfate ions and generating holes in the group III nitride, thereby etching the group III nitride, wherein in the etching of the group III nitride, the etching solution remains acidic during a period for etching the group III nitride by making the etching solution acidic at a start of etching the group III nitride, and the etching is performed, with a resist mask formed on the surface.

Abstract: A semiconductor substrate in includes a buffer layer and a first crystalline layer. A bandgap of the first crystalline layer is smaller than a bandgap of a second layer. When a semiconductor wafer is formed as a transistor wafer, a channel of a transistor is formed at or near an interface between the first crystalline layer and the second layer. With a first electrode and a second electrode provided and a third electrode provided, when space charge redistribution, for emitting electrons and holes from a bandgap of a crystal positioned in the spatial region, is achieved by applying negative voltage to the third electrode or by applying positive voltage to the second electrode with the first electrode serving as a reference, an electron emission speed in the space charge redistribution is higher than a hole emission speed.

Abstract: A semiconductor substrate in includes a buffer layer and a first crystalline layer. A bandgap of the first crystalline layer is smaller than a bandgap of a second layer. When a semiconductor wafer is formed as a transistor wafer, a channel of a transistor is formed at or near an interface between the first crystalline layer and the second layer. With a first electrode and a second electrode provided and a third electrode provided, when space charge redistribution, for emitting electrons and holes from a bandgap of a crystal positioned in the spatial region, is achieved by applying negative voltage to the third electrode or by applying positive voltage to the second electrode with the first electrode serving as a reference, an electron emission speed in the space charge redistribution is higher than a hole emission speed.

Abstract: To provide a semiconductor wafer having a wafer, a compound semiconductor layer, a first insulating layer and a second insulating layer, wherein in the depth direction, oxygen atoms and nitrogen atoms are continuously distributed, the number of the nitrogen atoms along the depth direction shows its maximum in the first insulating layer, the total number of third atoms and fourth atoms along the depth direction becomes the largest in the compound semiconductor layer, the number of the oxygen atoms at the interface between the compound semiconductor layer and the first insulating layer is smaller than the number of the oxygen atoms at the interface between the first insulating layer and the second insulating layer.

Abstract: Provided is a technique capable of realizing an insulated gate (MIS-type) P-HEMT structure with good transistor characteristics such as an improved carrier mobility of a channel layer and a reduced influence from interface states. A semiconductor wafer includes a base wafer, a first crystalline layer, and an insulating layer. The base wafer, the first crystalline layer, and the insulating layer are stacked in the order of the base wafer, the first crystalline layer, and the insulating layer. The first crystalline layer is made of InxGa1-xAs (0.35?x?0.43) that can pseudo-lattice-match with GaAs or AlGaAs. The first crystalline layer is usable as a channel layer of a field effect transistor, and the insulating layer is usable as a gate insulating layer of the field effect transistor.

Abstract: To provide a semiconductor wafer having a wafer, a compound semiconductor layer, a first insulating layer and a second insulating layer, wherein in the depth direction, oxygen atoms and nitrogen atoms are continuously distributed, the number of the nitrogen atoms along the depth direction shows its maximum in the first insulating layer, the total number of third atoms and fourth atoms along the depth direction becomes the largest in the compound semiconductor layer, the number of the oxygen atoms at the interface between the compound semiconductor layer and the first insulating layer is smaller than the number of the oxygen atoms at the interface between the first insulating layer and the second insulating layer.