Patents by Inventor Noboru Kosugi
Noboru Kosugi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060022691Abstract: It is able to restrict increase of a chip area even if the pad pitch is reduced and the pad length is increased in a semiconductor device by arranging pads (4, 5), comprising electrically connected first and second regions having different number of wiring layers, above an I/O circuit (2).Type: ApplicationFiled: October 4, 2005Publication date: February 2, 2006Applicant: FUJITSU LIMITEDInventors: Takanori Watanabe, Masashi Takase, Noboru Kosugi
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Patent number: 6934919Abstract: A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).Type: GrantFiled: March 9, 2004Date of Patent: August 23, 2005Assignee: Fujitsu LimitedInventors: Noboru Yokota, Hisayoshi Oba, Noboru Kosugi, Munehiro Tahara
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Patent number: 6925615Abstract: A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).Type: GrantFiled: February 8, 2002Date of Patent: August 2, 2005Assignee: Fujitsu LimitedInventors: Noboru Yokota, Hisayoshi Oba, Noboru Kosugi, Munehiro Tahara
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Patent number: 6886142Abstract: A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).Type: GrantFiled: February 8, 2002Date of Patent: April 26, 2005Assignee: Fujitsu LimitedInventors: Noboru Yokota, Hisayoshi Oba, Noboru Kosugi, Munehiro Tahara
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Publication number: 20040172606Abstract: A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).Type: ApplicationFiled: March 9, 2004Publication date: September 2, 2004Applicant: FUJITSU LIMITEDInventors: Noboru Yokota, Hisayoshi Oba, Noboru Kosugi, Munehiro Tahara
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Patent number: 6555853Abstract: A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).Type: GrantFiled: October 27, 1999Date of Patent: April 29, 2003Assignee: Fujitsu LimitedInventors: Noboru Yokota, Hisayoshi Oba, Noboru Kosugi, Munehiro Tahara
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Publication number: 20030062632Abstract: A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).Type: ApplicationFiled: October 27, 1999Publication date: April 3, 2003Inventors: NOBORU YOKOTA, HISAYOSHI OBA, NOBORU KOSUGI, MUNEHIRO TAHARA
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Publication number: 20020087941Abstract: A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).Type: ApplicationFiled: February 8, 2002Publication date: July 4, 2002Applicant: FUJITSU LIMITEDInventors: Noboru Yokota, Hisayoshi Oba, Noboru Kosugi, Munehiro Tahara
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Publication number: 20020084457Abstract: A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).Type: ApplicationFiled: February 8, 2002Publication date: July 4, 2002Applicant: FUJITSU LIMITEDInventors: Noboru Yokota, Hisayoshi Oba, Noboru Kosugi, Munehiro Tahara
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Patent number: 5281835Abstract: A semi-custom integrated circuit comprises a basic cell array comprising a plurality of basic cells aligned in a first direction, the basic cells comprising a transistor unit, a capacitor unit and a resistor unit arranged in a second direction perpendicular to the first direction. The transistor unit is positioned between the capacitor unit and the resistor unit. The transistor unit has a terminal portion for connection of wiring, the capacitor unit having a terminal portion for connection of wiring, the resistor unit having a terminal portion for connection of wiring. The terminal portions of said transistor unit, capacitor unit and resistor unit are aligned along a line.Type: GrantFiled: January 27, 1992Date of Patent: January 25, 1994Assignee: Fujitsu LimitedInventors: Masayoshi Tomita, Tadahiro Saitoh, Kiyokazu Hasegawa, Noboru Kosugi
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Patent number: 5052505Abstract: A load cell has a cantilever-type load-sensitive element with an upper beam and a lower beam, each having formed thereon a pair of strain-generating parts which generates a strain corresponding to an applied load. Only one of these two beams has an indented part formed on its surface and strain-detecting elements are attached to its bottom surface at positions corresponding to the strain-generating parts. A moisture-proof sheet is attached to the beam to completely seal the interior of this indented part to protect the strain-detecting elements from humidity and moisture.Type: GrantFiled: May 24, 1990Date of Patent: October 1, 1991Assignee: Ishida Scales Mfg. Co., Ltd.Inventors: Kazufumi Naito, Seiji Nishide, Hiroyuki Konishi, Noboru Kosugi