Patents by Inventor Noboru Mizuguchi

Noboru Mizuguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7940799
    Abstract: In order to cope with format conversion of user data, the bit rate value and VBV (Video Buffering Verifier) buffer size value in a sequence header of an input code and the VBV delay value in a picture header of the input code are modified to obtain an intermediate code (305 to 309), and additional information (300) is generated for distinguishing GOP (Group of Pictures) user data (307) from the other main data. A VBV buffer simulation is performed using this additional information (300) to multiplex the GOP user data in a picture user data region to a data amount such that the operation does not fail, whereby an output code is generated.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: May 10, 2011
    Assignee: Panasonic Corporation
    Inventors: Akihiro Watabe, Noboru Mizuguchi, Eiji Miyagoshi, Takayuki Morishige
  • Publication number: 20090129759
    Abstract: A format converter for converting the format of input contents data from a first format standard to a second format standard includes an extraction section (30), a judgment section (40), a determination section (60) and a conversion section (70). The extraction section (30) extracts information related to encoding of the input contents data. The judgment section (40) judges whether or not the contents data satisfies a constraint placed by the second format standard based on the extracted information. The determination section (60) determines whether or not decoding of the contents data is necessary for the format conversion based on the judgment result. The conversion section (70) performs the format conversion by converting data structure when it is determined that the decoding is unnecessary.
    Type: Application
    Filed: November 28, 2006
    Publication date: May 21, 2009
    Inventors: Noboru Mizuguchi, Akihiro Watabe
  • Publication number: 20090109810
    Abstract: A recording/reproduction apparatus includes a first recording medium (a flash memory) having a first time that is required for the first recording medium to go from a low-power consumption state to a state in which recorded video data can be read out, and a second recording medium (an HDD or a DVD drive) having a second time that is required for the second recording medium to go from a low-power consumption state to a state in which recorded video data can be read out, where the second time is longer than the first time. When a video content is reproduced from the second recording medium in the low-power consumption state, the first recording medium is caused to go to a readable state while the second recording medium is not in a readable state, and a leading portion of the content is reproduced from the first recording medium.
    Type: Application
    Filed: September 3, 2008
    Publication date: April 30, 2009
    Inventors: Masayuki Fukuyama, Eiji Miyagoshi, Akihiro Watabe, Akihiko Otani, Noboru Mizuguchi, Yuichiro Aihara
  • Publication number: 20060153290
    Abstract: In order to cope with format conversion of user data, the bit rate value and VBV (Video Buffering Verifier) buffer size value in a sequence header of an input code and the VBV delay value in a picture header of the input code are modified to obtain an intermediate code (305 to 309), and additional information (300) is generated for distinguishing GOP (Group of Pictures) user data (307) from the other main data. A VBV buffer simulation is performed using this additional information (300) to multiplex the GOP user data in a picture user data region to a data amount such that the operation does not fail, whereby an output code is generated.
    Type: Application
    Filed: February 2, 2004
    Publication date: July 13, 2006
    Inventors: Akihiro Watabe, Noboru Mizuguchi, Eiji Miyagoshi, Takayuki Morishige
  • Publication number: 20020196855
    Abstract: An external memory interface in a DVMPEG converter inputs/outputs DV data, which has been decoded by a DV decoder, to/from an external memory. Moreover, a format converter receives data, which is read out from the external memory via the external memory interface, and converts the format thereof from a DV format to an MPEG format. Then, an MPEG encoder encodes the DV data whose format has been converted so as to produce MPEG data. Thus, it is possible to provide a DVMPEG converter having a small circuit scale.
    Type: Application
    Filed: May 7, 2002
    Publication date: December 26, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Eiji Miyagoshi, Akihiro Watabe, Takayuki Morishige, Noboru Mizuguchi
  • Patent number: 6064796
    Abstract: A signal conversion recording method applies a signal recording method whereby a video signal converted to a frame rate greater than the frame rate of the signal source by repeating particular fields plural times is converted to an intermediate signal having a frame rate substantially equal to the frame rate of the original signal source by deleting these repeated redundant fields. This intermediate signal is compression coded to obtain the recording signal, and the recording signal is recorded to a recording medium together with a repeat first field flag RFF declaring whether a field was deleted, and a top field first flag TFF declaring which of the two fields in the each of the resulting frames is first on the time-base, is wherein when plural logical recording periods are provided on a single recording medium, the video signal is converted to the recording signal so that the flags hold particular values at the start and end of each recording period.
    Type: Grant
    Filed: February 4, 1998
    Date of Patent: May 16, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiko Nakamura, Kazuhiro Tsuga, Takumi Hasebe, Yoshihiro Mori, Yasuhiko Yamane, Noboru Mizuguchi
  • Patent number: 6044115
    Abstract: An image coding method and apparatus for transforming and quantizing an image to produce transformed and quantized coefficients. The coefficients are coded and a complexity index value is obtained from the input image to calculate local characteristic values used to modify the quantization scale. In this manner, rate control is obtained on the basis of the local characteristics of the image, whereby the quality of the coded image and the precision of the rate control is improved.
    Type: Grant
    Filed: December 9, 1997
    Date of Patent: March 28, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuyoshi Horiike, Noboru Mizuguchi
  • Patent number: 5745645
    Abstract: A signal conversion recording method applies a signal recording method whereby a video signal converted to a frame rate greater than the frame rate of the signal source by repeating particular fields plural times is converted to an intermediate signal having a frame rate substantially equal to the frame rate of the original signal source by deleting these repeated redundant fields. This intermediate signal is compression coded to obtain the recording signal, and the recording signal is recorded to a recording medium together with a repeat first field flag RFF declaring whether a field was deleted, and a top field first flag TFF declaring which of the two fields in the each of the resulting frames is first on the time-base, wherein when plural logical recording periods are provided on a single recording medium, said video signal is converted to the recording signal so that said flags hold particular values at the start and end of each recording period.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: April 28, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiko Nakamura, Kazuhiro Tsuga, Takumi Hasebe, Yoshihiro Mori, Yasuhiko Yamane, Noboru Mizuguchi
  • Patent number: 5444711
    Abstract: An HDTV signal transmission system for sending a 10-bit-parallel YPbPr-format HDTV signal converted to ten C4 containers, and further to the SDH (a new synchronous digital network) STM-16 frame for transmission based on CCITT recommendations. The system includes a transmitter and receiver. The transmitter has time dividers for time-based dividing the HDTV signal into eight separated video signals, a C4 container device for multiplexing the eight separated video signals to ten C4 containers, and a STM-16 framing device for reformatting the ten C4 containers to the STM-16 frame. The receiver has an STM-16 deframing device for separating the ten C4 containers from the STM-16 frame, a C4 de-container device for demultiplexing the ten C4 containers to eight separated video signals, and time-division multiplexers for time-division multiplexing the separated video signals to the 10-bit-parallel YPbPr-format HDTV signal.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: August 22, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Noboru Mizuguchi, Kiyoshi Uchimura, Masatoshi Tanaka, Seiho Kitaji
  • Patent number: 5442405
    Abstract: A frame synchronizing apparatus is disclosed which includes a serial-parallel converter for converting input serial data into parallel data of a plurality of channels; a plurality of intra-channel synchronization detecting circuits each for detecting a synchronization pattern and a pseudo-synchronization pattern in one channel, and generating a channel synchronization detect signal and a pseudo-synchronization detect signal in one channel; a plurality of bit-shift error pattern detecting circuits each for detecting a bit-shift error pattern in one channel, and generating a bit-shift error pattern signal in one channel; a synchronization/bit-shift error detecting circuit for detecting a synchronization between channels and specifying the amount of erroneously shifted bits, and generating a frame synchronization detect signal and bit-shift error detect signals; and a bit-shift signal generating circuit for calculating the number of erroneously shifted bits in the serial-parallel converter based on the bit-shift
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: August 15, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenshi Taniguchi, Masatoshi Tanaka, Noboru Mizuguchi, Kiyoshi Uchimura