Patents by Inventor Noboru Mori

Noboru Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing semiconductor device that uses both a normal photomask and a phase shift mask for defining interconnect patterns
    Patent number: 8084279
    Abstract: According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps. A step of preparing a phase shift mask and a normal photomask. A step of stacking a first wiring layer on a semiconductor substrate, and further stacking, on the first wiring layer, a second wiring layer. The second wiring layer includes a second wiring and third wiring. A step of stacking an interlayer insulating film on the second wiring layer. A step of forming, in the interlayer insulating film, a first opening in which the second wiring is exposed, and a second opening in which the third wiring is exposed by photolithography using the normal photomask. A step of burying a metal in the first opening and the second opening. A step of providing a pad to be overlaid on the first and second openings.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: December 27, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuo Kasaoka, Kiyohiko Sakakibara, Noboru Mori, Kazunobu Miki
  • METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE THAT USES BOTH A NORMAL PHOTOMASK AND A PHASE SHIFT MASK FOR DEFINING INTERCONNECT PATTERNS
    Publication number: 20100159690
    Abstract: According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps. A step of preparing a phase shift mask and a normal photomask. A step of stacking a first wiring layer on a semiconductor substrate, and further stacking, on the first wiring layer, a second wiring layer. The a second wiring layer includes a second wiring and a third wiring. A step of stacking an interlayer insulating film on the second wiring layer. A step of forming, in the interlayer insulating film, a first opening in which the second wiring is exposed, and a second opening in which the third wiring is exposed by photolithography using the normal photomask. A step of burying a metal in the first opening and the second opening. A step of providing a pad to be overlaid on the first and second openings.
    Type: Application
    Filed: March 9, 2010
    Publication date: June 24, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Tatsuo Kasaoka, Kiyohiko Sakakibara, Noboru Mori, Kazunobu Miki
  • Method of manufacturing semiconductor device that uses both a normal photomask and a phase shift mask for defining interconnect patterns
    Patent number: 7696081
    Abstract: According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps. A step of preparing a phase shift mask and a normal photomask. A step of stacking a first wiring layer on a semiconductor substrate, and further stacking, on the first wiring layer, a second wiring layer. The a second wiring layer includes a second wiring and a third wiring. A step of stacking an interlayer insulating film on the second wiring layer. A step of forming, in the interlayer insulating film, a first opening in which the second wiring is exposed, and a second opening in which the third wiring is exposed by photolithography using the normal photomask. A step of burying a metal in the first opening and the second opening. A step of providing a pad to be overlaid on the first and second openings.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: April 13, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Tatsuo Kasaoka, Kiyohiko Sakakibara, Noboru Mori, Kazunobu Miki
  • Semiconductor device and method of manufacturing semiconductor device
    Publication number: 20080217786
    Abstract: According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps. A step of preparing a phase shift mask and a normal photomask. A step of stacking a first wiring layer on a semiconductor substrate, and further stacking, on the first wiring layer, a second wiring layer. The a second wiring layer includes a second wiring and a third wiring. A step of stacking an interlayer insulating film on the second wiring layer. A step of forming, in the interlayer insulating film, a first opening in which the second wiring is exposed, and a second opening in which the third wiring is exposed by photolithography using the normal photomask. A step of burying a metal in the first opening and the second opening. A step of providing a pad to be overlaid on the first and second openings.
    Type: Application
    Filed: January 30, 2008
    Publication date: September 11, 2008
    Inventors: Tatsuo Kasaoka, Kiyohiko Sakakibara, Noboru Mori, Kazunobu Miki
  • Method of manufacturing composite electronic component
    Patent number: 6141847
    Abstract: A ceramic substrate 1 made of magnetic substance on which an inductor 2 is formed is prepared. A ceramic substrate 3 made of dielectric substance on which a capacitor 4 is formed is also prepared. An intermediate layer 5 made of lass paste is printed on the inductor 2 and the capacitor 4. After debinding the substrates 1 and 3 independently, both the substrates are filed with the intermediate layer 5 therebetween so that both the substrates may be glued and integrated. As such, because the debinding process is provided before filing, less gas is generated in firing, and as a result, voids are restrained from occurring.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: November 7, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masayuki Mizuno, Masaaki Hayama, Kazuhiro Miura, Noboru Mori, Akira Hashimoto, Mitsuteru Yamada
  • Method and system for recycling washing liquids and the heat contained therein
    Patent number: 4451298
    Abstract: A system for recovery and recycling of a washing liquid and heat contained in the washings discharged from a metal surface treatment process comprises a hot water washing tank with an associated cushion tank, a cold water washing tank with an associated cushion tank, a heat exchanger, an ion exchanger and a filter. The second-mentioned cushion tank is in communication with the hot water washing tank through the heat exchanger, while the first-mentioned cushion tank is in communication with the cold water washing tank through the filter, the heat exchanger and the ion exchanger.
    Type: Grant
    Filed: December 8, 1981
    Date of Patent: May 29, 1984
    Assignee: Kabushiki Kaisha Sanshin Seisakusho
    Inventors: Aisaburo Yagishita, Noboru Mori, Kinshiro Kusumi, Yoshio Tsugi