Abstract: A semiconductor device includes: a semiconductor substrate having a cell region in which a device is provided, and a termination region provided around the cell region; a first insulating film provided on the semiconductor substrate in the termination region and having a plurality of openings; a plurality of metal electrodes provided in the termination region and connected to the semiconductor substrate via the plurality of openings; and a second insulating film having lower coefficient of moisture absorption than that of the first insulating film and covering the first insulating film and the plurality of metal electrodes, wherein the second insulating film is in direct contact with the semiconductor substrate in a region from the outermost electrode of the plurality of metal electrodes to an end part of the semiconductor substrate.

Abstract: A semiconductor device includes: a semiconductor substrate having a cell region in which a device is provided, and a termination region provided around the cell region; a first insulating film provided on the semiconductor substrate in the termination region and having a plurality of openings; a plurality of metal electrodes provided in the termination region and connected to the semiconductor substrate via the plurality of openings; and a second insulating film having lower coefficient of moisture absorption than that of the first insulating film and covering the first insulating film and the plurality of metal electrodes, wherein the second insulating film is in direct contact with the semiconductor substrate in a region from the outermost electrode of the plurality of metal electrodes to an end part of the semiconductor substrate.

Abstract: A semiconductor device includes: a semiconductor substrate having a cell region in which a device is provided, and a termination region provided around the cell region; a first insulating film provided on the semiconductor substrate in the termination region and having a plurality of openings; a plurality of metal electrodes provided in the termination region and connected to the semiconductor substrate via the plurality of openings; and a second insulating film having lower coefficient of moisture absorption than that of the first insulating film and covering the first insulating film and the plurality of metal electrodes, wherein the second insulating film is in direct contact with the semiconductor substrate in a region from the outermost electrode of the plurality of metal electrodes to an end part of the semiconductor substrate.

Abstract: A semiconductor device includes: a semiconductor substrate having a cell region in which a device is provided, and a termination region provided around the cell region; a first insulating film provided on the semiconductor substrate in the termination region and having a plurality of openings; a plurality of metal electrodes provided in the termination region and connected to the semiconductor substrate via the plurality of openings; and a second insulating film having lower coefficient of moisture absorption than that of the first insulating film and covering the first insulating film and the plurality of metal electrodes, wherein the second insulating film is in direct contact with the semiconductor substrate in a region from the outermost electrode of the plurality of metal electrodes to an end part of the semiconductor substrate.

Abstract: A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of which the cross sectional form is rectangular are layered.

Abstract: To provide a manufacturing method of a semiconductor device which can improve the reliability of the semiconductor device. A first insulating film for covering a semiconductor element formed in a semiconductor substrate is formed by a thermal CVD method or the like which has a good embedding property. A second insulating film is formed to cover the first insulating film by a plasma CVD method which has excellent humidity resistance. A plug is formed to penetrate the first insulating film and the second insulating film. A third insulating film comprised of a low-k film having a relatively low dielectric constant is formed over the second insulating film. A wiring is formed in the third insulating film by a damascene technique to be electrically coupled to the plug.

Abstract: A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of which the cross sectional form is rectangular are layered.

Abstract: A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of which the cross sectional form is rectangular are layered.

Abstract: A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of which the cross sectional form is rectangular are layered.

Abstract: A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of which the cross sectional form is rectangular are layered.

Abstract: To provide a manufacturing method of a semiconductor device which can improve the reliability of the semiconductor device. A first insulating film for covering a semiconductor element formed in a semiconductor substrate is formed by a thermal CVD method or the like which has a good embedding property. A second insulating film is formed to cover the first insulating film by a plasma CVD method which has excellent humidity resistance. A plug is formed to penetrate the first insulating film and the second insulating film. A third insulating film comprised of a low-k film having a relatively low dielectric constant is formed over the second insulating film. A wiring is formed in the third insulating film by a damascene technique to be electrically coupled to the plug.

Abstract: A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of which the cross sectional form is rectangular are layered.

Abstract: A semiconductor device includes a low dielectric constant film having a copper interconnection formed therein, a silicon oxide film arranged above the low dielectric constant film, a surface protection film arranged above the silicon oxide film, a sealing ring formed to surround a circuit forming region, and a groove portion formed outside the sealing ring when viewed two-dimensionally. The groove portion is formed such that its bottom portion is located above the low dielectric constant film and such that the bottom portion is located below an upper end of the copper interconnection.

Abstract: A metal layer (7), a metallic compound layer (8) and a metal layer (9) are stacked in this order when viewed from the side of a first copper interconnect line (2) and an interlayer insulating film (5) to constitute a second conductive barrier layer (20). As the material for the metal layers (7) and (9), an element having an atomic weight higher than that of copper such as tungsten (W) or tantalum (Ta) is applicable. A second copper interconnect line (6) is conductively connected to the first copper interconnect line (2) at a contact hole (12) through the second conductive barrier layer (20). As the ratio of the volume of the second copper interconnect line (6) at the region for filling a trench (11) to the volume of the second copper interconnect line (6) at the region for filling the contact hole (12) increases, tensile stress to be concentrated at the contact hole (12) becomes greater. As a result, a void is likely to be generated in the contact hole (12).

Abstract: A method of manufacturing a semiconductor device is obtained which is capable of evading generation of a short circuit between wirings in an upper wiring layer even if a part of an upper surface of an FSG film is exposed by variations in a production step. After a USG film (4) is deposited to a thickness of 1 &mgr;m over an entire surface of an FSG film (3), the USG film (4) is polished and removed by a thickness of 900 nm from an upper surface thereof by the CMP method. At this time, a part of an upper surface of the FSG film (3) is exposed by variations in a production step. Next, the surface of the interlayer dielectric film (50) is cleaned with a cleaning liquid whose etching rate to the FSG film (3) and etching rate to the USG film (5) are substantially the same. Such a cleaning liquid may be, for example, an ammonia hydrogen peroxide mixture of NH4OH:H2O2:H2O=1:1:20. The structure shown in FIG.

Abstract: A second-level wire is formed by a dual damascene process in a insulating film. In an upper surface of the first insulating film a metal film is formed and serves as a first electrode of an MIM-type capacitor. A second insulating films has a structure in which a plurality of insulating films are layered on a second interconnection layer, in this order. In a first insulating film of the plurality of insulating films, a second electrode of the MIM-type capacitor is formed. The second electrode has a first metal film formed on a second insulating film of the plurality of the insulating films and a second metal film is formed on the first metal film. A portion of the second insulating film which is sandwiched between the first electrode and the second electrode of the MIM-type capacitor serves as a capacitor dielectric film of the MIM-type capacitor.

Abstract: A wire width and a wiring space of each of signal wires 1 and ground/power wires 2 are determined to be a wire width W1 (the minimum wire width) and a wiring space S1, respectively. A wire width and a wiring space of the via-hole neighboring region 1a or 2a are determined to be a wire width W2 (>W1) and a wiring space S2 (<S1), respectively. The wire widths W1 and W2 and the wiring spaces S1 and S2 are respectively determined so as to maintain the minimum wiring pitch P. The wiring space S1 is determined also so as to satisfy {S1/P≧0.6}. Further, the signal wires 1 and the ground/power wires 2 have the same wire thickness of a wire thickness T1 which allows an aspect ratio (T1/W1) to be equal to, or higher than, 2.

Abstract: A metal layer (7), a metallic compound layer (8) and a metal layer (9) are stacked in this order when viewed from the side of a first copper interconnect line (2) and an interlayer insulating film (5) to constitute a second conductive barrier layer (20). As the material for the metal layers (7) and (9), an element having an atomic weight higher than that of copper such as tungsten (W) or tantalum (Ta) is applicable. A second copper interconnect line (6) is conductively connected to the first copper interconnect line (2) at a contact hole (12) through the second conductive barrier layer (20). As the ratio of the volume of the second copper interconnect line (6) at the region for filling a trench (11) to the volume of the second copper interconnect line (6) at the region for filling the contact hole (12) increases, tensile stress to be concentrated at the contact hole (12) becomes greater. As a result, a void is likely to be generated in the contact hole (12).

Abstract: A wire width and a wiring space of each of signal wires 1 and ground/power wires 2 are determined to be a wire width W1 (the minimum wire width) and a wiring space S1, respectively. A wire width and a wiring space of the via-hole neighboring region 1a or 2a are determined to be a wire width W2 (>W1) and a wiring space S2 (<S1), respectively. The wire widths W1 and W2 and the wiring spaces S1 and S2 are respectively determined so as to maintain the minimum wiring pitch P. The wiring space S1 is determined also so as to satisfy {S1/P≧0.6}. Further, the signal wires 1 and the ground/power wires 2 have the same wire thickness of a wire thickness T1 which allows an aspect ratio (T1/W1) to be equal to, or higher than, 2.

Abstract: A metal layer (7), a metallic compound layer (8) and a metal layer (9) are stacked in this order when viewed from the side of a first copper interconnect line (2) and an interlayer insulating film (5) to constitute a second conductive barrier layer (20). As the material for the metal layers (7) and (9), an element having an atomic weight higher than that of copper such as tungsten (W) or tantalum (Ta) is applicable. A second copper interconnect line (6) is conductively connected to the first copper interconnect line (2) at a contact hole (12) through the second conductive barrier layer (20). As the ratio of the volume of the second copper interconnect line (6) at the region for filling a trench (11) to the volume of the second copper interconnect line (6) at the region for filling the contact hole (12) increases, tensile stress to be concentrated at the contact hole (12) becomes greater. As a result, a void is likely to be generated in the contact hole (12).