Abstract: A wire bonding method involves bonding a wire in order at a first bonding point and a second bonding point; raising a capillary, through which the wire is inserted, on the second bonding point; cutting the wire by closing a clamper provided above the capillary at a time when the capillary has reached a prescribed height; and measuring a load incurred on the wire at a time of cutting of the wire.

Abstract: A wire bonding method involves bonding a wire in order at a first bonding point and a second bonding point; raising a capillary, through which the wire is inserted, on the second bonding point; cutting the wire by closing a clamper provided above the capillary at a time when the capillary has reached a prescribed height; and measuring a load incurred on the wire at a time of cutting of the wire

Abstract: A semiconductor device has a plurality of bare chips stacked on at least one of first and second main surfaces oppositely arranged on a support substrate, spacers arranged between two bare chips arranged adjacently in up and down direction among the plurality of bare chips, and inner leads which are arranged at both sides in a horizontal direction of the support substrate and are connected to pads of the bare chips via bonding wires, wherein the bonding wires which connect the pads of the bare chips at one end side of the spacers to the corresponding inner leads, are arranged not to contact the bare chip at the other end side of the same spacer.

Abstract: A wire bonding apparatus comprising: a capillary configured to have inserted therethrough a wire; a damper provided above the capillary and able to clamp hold the wire; and a load sensor configured to measure load incurred on the wire.

Abstract: A semiconductor package includes a circuit board having connection pads formed on a front and back surfaces, and a wiring network connected to these connection pads, as a package base. Metal bumps connected to at least part of the connection pads on the front and back surfaces via the wiring network are formed on the back surface of the circuit board as external connection terminals. One or a plurality of semiconductor elements electrically connected to the connection pad on the front surface side is or are mounted on a first element mounting part provided on the front surface side of the circuit board. One or plurality of semiconductor elements electrically connected to the connection pad on the back surface side is or are mounted on a second element mounting part provided on the back surface side of the circuit board.

Abstract: A semiconductor package includes a lead frame having an element mounting part and a lead part. A first semiconductor element and a second semiconductor element are sequentially stacked on a principal surface at least on one side of the element mounting part. An insulating resin layer serving as a second adhesive layer is filled between the first semiconductor element and the second semiconductor element. An element-side end portion of a first bonding wire connected to the first semiconductor element is buried in the insulating resin layer.

Abstract: A semiconductor device has a plurality of bare chips stacked on at least one of first and second main surfaces oppositely arranged on a support substrate, spacers arranged between two bare chips arranged adjacently in up and down direction among the plurality of bare chips, and inner leads which are arranged at both sides in a horizontal direction of the support substrate and are connected to pads of the bare chips via bonding wires, wherein the bonding wires which connect the pads of the bare chips at one end side of the spacers to the corresponding inner leads, are arranged not to contact the bare chip at the other end side of the same spacer.