Abstract: There is provided a testing apparatus including a plurality of test units, a storage that is shared by the plurality of test units, where the storage stores therein wafers under test to be tested by the plurality of test units, a transport mechanism that transports the wafers under test between the storage and each of the plurality of test units, a mainframe that specifies a test procedure for each of the plurality of test units, a power source that is shared by the plurality of test units, where the power source supplies power to each of the plurality of test units, and a pressure source that is shared by the plurality of test units, where the pressure source supplies a pressure to each of the plurality of test units.

Abstract: There is provided a testing apparatus including a plurality of test units, a storage that is shared by the plurality of test units, where the storage stores therein wafers under test to be tested by the plurality of test units, a transport mechanism that transports the wafers under test between the storage and each of the plurality of test units, a mainframe that specifies a test procedure for each of the plurality of test units, a power source that is shared by the plurality of test units, where the power source supplies power to each of the plurality of test units, and a pressure source that is shared by the plurality of test units, where the pressure source supplies a pressure to each of the plurality of test units.

Abstract: A memory testing method and apparatus are provided, which can test in short time a flash memory. In case of testing a flash memory having block function, in a memory testing method and apparatus in which a predetermined logical value is written in memory cells constituting each of blocks of the memory, the written logical value is read out from the memory cells to compare it with an expected value, and a decision that, when the read-out logical value and the expected value do not coincide with each other, such memory cell is a failure memory cell, a decision is rendered that, when the number of failure memory cells in each block reaches a predetermined number, such block is a bad block, and the test of such block is stopped.

Abstract: A memory block is subject to an erasure operation by a batch operation. Subsequently, a read-out test is conducted upon the memory block to count the number of unerased memory cells. If the count FN is equal to or greater than a given number TF, a plurality of erasure operations are conducted consecutively next. If FN<TF, a single erasure operation is conducted next, subsequently followed by a read-out test. The erasure operations and the read-out tests are repeated.

Abstract: A testing method which reduces a testing time for a flash memory is proposed.

Abstract: A memory testing method and apparatus are provided, which can test in short time a flash memory. In case of testing a flash memory having block function, in a memory testing method and apparatus in which a predetermined logical value is written in memory cells constituting each of blocks of the memory, the written logical value is read out from the memory cells to compare it with an expected value, and a decision that, when the read-out logical value and the expected value do not coincide with each other, such memory cell is a failure memory cell, a decision is rendered that, when the number of failure memory cells in each block reaches a predetermined number, such block is a bad block, and the test of such block is stopped.

Abstract: A failure analysis of a semiconductor memory compares data written into and out of each cell of the semiconductor memory. When there is a disagreement, a "1" is written into a failure analysis memory. A disagreement signal is applied as a write command to column and row address fail count memories and is counted by a fail counter. The column address and row address fail count memories receive the column and row addresses, respectively. When the write command is applied to the column and row address fail count memories, the number of defective cells is read out of the memory addresses by a read modify write operation. A 1 is added by column and row adders to the number of defective cells read out, and the results are written into the column and row address fail count memories. The number of defective cells is read out of the column address fail count memory and compared with a number of row spare lines of the memory under test.

Abstract: A logic circuit part, which is composed of a flip-flop group and a combinational circuit and performs a sequential logic operation, is added with a specify circuit for selectively specifying desired flip-flop circuits in the flip-flop group and a write circuit for applying a set or reset signal to the flip-flop circuits selectively specified by the specify circuit. Each flip-flop circuit includes: a flip-flop for writing input data in response to a system clock; a first AND gate which, when the flip-flop circuit is selectively specified by the specify circuit, passes therethrough the set signal to set the flip-flop; a second AND gate which, when the flip-flop circuit is selectively specified by the specify circuit, passes therethrough the reset signal to reset the flip-flop; and a third and gate which, when the flip-flop circuit is selectively specified by the specify circuit, passes therethrough the output logic of the flip-flop to the outside.

Abstract: In a main pattern memory are stored an increment command pattern and an enable control pattern in addition to test patterns. The main pattern memory is read out with an address from an address control circuit. The increment command pattern thus read out of the main pattern memory instructs incrementing of an address pointer, and a partial pattern memory is read out according to the contents of the address pointer. In accordance with the enable control pattern read out of the main pattern memory, a gate circuit is controlled to open, through which the output of the partial pattern memory is passed, and bits of the passed output are each ORed, by an OR circuit, with the corresponding bits of the test pattern read out of the main pattern memory, providing the ORed output as a test pattern.