Abstract: According to one embodiment, a semiconductor storage device includes: a NAND string with a first set of memory cells including a first memory cell; and a second set of memory cells including a second memory cell disposed above the first memory cell. The number of memory cells included in the first set is different from that of memory cells included in the second set. During a program verify operation when a data item of a level is written to a memory cell of the first set and a memory cell of the second set, a first verify voltage is applied to the gate of the memory cell of the first set and a second verify voltage different from the first verify voltage is applied to the gate of the memory cell of the second set.

Abstract: According to one embodiment, a semiconductor storage device includes: a NAND string with a first set of memory cells including a first memory cell; and a second set of memory cells including a second memory cell disposed above the first memory cell. The number of memory cells included in the first set is different from that of memory cells included in the second set. During a program verify operation when a data item of a level is written to a memory cell of the first set and a memory cell of the second set, a first verify voltage is applied to the gate of the memory cell of the first set and a second verify voltage different from the first verify voltage is applied to the gate of the memory cell of the second set.

Abstract: According to one embodiment, a semiconductor storage device includes: a NAND string with a first set of memory cells including a first memory cell; and a second set of memory cells including a second memory cell disposed above the first memory cell. The number of memory cells included in the first set is different from that of memory cells included in the second set. During a program verify operation when a data item of a level is written to a memory cell of the first set and a memory cell of the second set, a first verify voltage is applied to the gate of the memory cell of the first set and a second verify voltage different from the first verify voltage is applied to the gate of the memory cell of the second set.

Abstract: A semiconductor memory device includes a plurality of memory cells, a plurality of word lines, including a word line that is connected to a group of the memory cells, and a control circuit configured to execute a write operation on the memory cells of the group. The write operation includes multiple program loops including a first program loop and a second program loop that is executed at a later time than the first program loop, and for each subsequent program loop, a program voltage that is applied to the first word line is increased from that of a current program loop. The program voltage is increased by a first amount from that of the current program loop if the next program loop is the first program loop and by a second amount that is less than the first amount if the next program loop is the second program loop.

Abstract: According to one embodiment, a semiconductor storage device includes: a NAND string with a first set of memory cells including a first memory cell; and a second set of memory cells including a second memory cell disposed above the first memory cell. The number of memory cells included in the first set is different from that of memory cells included in the second set. During a program verify operation when a data item of a level is written to a memory cell of the first set and a memory cell of the second set, a first verify voltage is applied to the gate of the memory cell of the first set and a second verify voltage different from the first verify voltage is applied to the gate of the memory cell of the second set.

Abstract: According to one embodiment, a semiconductor storage device includes: a NAND string with a first set of memory cells including a first memory cell; and a second set of memory cells including a second memory cell disposed above the first memory cell. The number of memory cells included in the first set is different from that of memory cells included in the second set. During a program verify operation when a data item of a level is written to a memory cell of the first set and a memory cell of the second set, a first verify voltage is applied to the gate of the memory cell of the first set and a second verify voltage different from the first verify voltage is applied to the gate of the memory cell of the second set.

Abstract: A semiconductor memory device includes a plurality of memory cells, a plurality of word lines, including a word line that is connected to a group of the memory cells, and a control circuit configured to execute a write operation on the memory cells of the group. The write operation includes multiple program loops including a first program loop and a second program loop that is executed at a later time than the first program loop, and for each subsequent program loop, a program voltage that is applied to the first word line is increased from that of a current program loop. The program voltage is increased by a first amount from that of the current program loop if the next program loop is the first program loop and by a second amount that is less than the first amount if the next program loop is the second program loop.

Abstract: According to one embodiment, a semiconductor storage device includes: a NAND string with a first set of memory cells including a first memory cell; and a second set of memory cells including a second memory cell disposed above the first memory cell. The number of memory cells included in the first set is different from that of memory cells included in the second set. During a program verify operation when a data item of a level is written to a memory cell of the first set and a memory cell of the second set, a first verify voltage is applied to the gate of the memory cell of the first set and a second verify voltage different from the first verify voltage is applied to the gate of the memory cell of the second set.

Abstract: A nonvolatile semiconductor memory device according to one embodiment includes a control circuit. The control circuit is configured to apply, when reading data of a first selected memory cell provided in a ROM area, a first read voltage to a first selected word line, and apply a first read pass voltage lower than a second read pass voltage to a first non-selected word line, thus allowing for the ROM area reading operation of reading a threshold voltage set in the first selected memory cell. The control circuit is configured to apply, when reading data of a second selected memory cell provided in a normal storage area, a second read voltage to a second selected word line, and apply the second read pass voltage to a second non-selected word line, thus allowing for a normal storage area reading operation of reading a threshold voltage set in the second selected memory cell.

Abstract: A nonvolatile semiconductor memory device according to one embodiment includes a control circuit. The control circuit is configured to apply, when reading data of a first selected memory cell provided in a ROM area, a first read voltage to a first selected word line, and apply a first read pass voltage lower than a second read pass voltage to a first non-selected word line, thus allowing for the ROM area reading operation of reading a threshold voltage set in the first selected memory cell. The control circuit is configured to apply, when reading data of a second selected memory cell provided in a normal storage area, a second read voltage to a second selected word line, and apply the second read pass voltage to a second non-selected word line, thus allowing for a normal storage area reading operation of reading a threshold voltage set in the second selected memory cell.

Abstract: A nonvolatile semiconductor memory device according to embodiment includes: a semiconductor substrate having an upper portion being partitioned into a plurality of semiconductor portions extending in a first direction; a charge storage film provided on the semiconductor portion; a word-line electrode provided on the semiconductor substrate and extending in a second direction intersecting with the first direction; and a pair of selection gate electrodes provided on both sides of the word-line electrode in the first direction on the semiconductor substrate and extending in the second direction, a shortest distance between a corner portion of each of the semiconductor portions and each of the selection gate electrodes being longer than a shortest distance between the corner portion of the semiconductor portion and the word-line electrode in a cross section parallel to the second direction.

Abstract: A nonvolatile semiconductor memory device according to embodiment includes: a semiconductor substrate having an upper portion being partitioned into a plurality of semiconductor portions extending in a first direction; a charge storage film provided on the semiconductor portion; a word-line electrode provided on the semiconductor substrate and extending in a second direction intersecting with the first direction; and a pair of selection gate electrodes provided on both sides of the word-line electrode in the first direction on the semiconductor substrate and extending in the second direction, a shortest distance between a corner portion of each of the semiconductor portions and each of the selection gate electrodes being longer than a shortest distance between the corner portion of the semiconductor portion and the word-line electrode in a cross section parallel to the second direction.

Abstract: In one embodiment, a nonvolatile semiconductor memory device includes a substrate, and a well region formed in the substrate. The device further includes device regions formed in the well region and defined by isolation trenches formed in the well region, the device regions extending in a first direction parallel to a principal surface of the substrate, and being adjacent to one another in a second direction that is perpendicular to the first direction. The device further includes isolation insulators buried in the isolation trenches to isolate the device regions from one another. The device further includes floating gates disposed on the device regions via gate insulators, and a control gate disposed on the floating gates via an intergate insulator. The device further includes first diffusion suppressing layers formed inside the respective device regions to divide each of the device regions into an upper device region and a lower device region.

Abstract: In one embodiment, a semiconductor memory device includes a semiconductor substrate, and isolation layers formed in a surface of the semiconductor substrate, and separating the semiconductor substrate into active areas, the isolation layers and the active areas being alternately arranged along a predetermined direction parallel to the surface of the semiconductor substrate, a height of upper surfaces of the isolation layers being lower than a height of an upper surface of the semiconductor substrate. The device further includes diffusion layers formed on surfaces of the active areas, and a stress liner formed on upper surfaces and side surfaces of the diffusion layers, and formed of a material having a lattice constant smaller than a lattice constant of a material formed of the semiconductor substrate.

Abstract: In one embodiment, a nonvolatile semiconductor memory device includes a substrate, and a well region formed in the substrate. The device further includes device regions formed in the well region and defined by isolation trenches formed in the well region, the device regions extending in a first direction parallel to a principal surface of the substrate, and being adjacent to one another in a second direction that is perpendicular to the first direction. The device further includes isolation insulators buried in the isolation trenches to isolate the device regions from one another. The device further includes floating gates disposed on the device regions via gate insulators, and a control gate disposed on the floating gates via an intergate insulator. The device further includes first diffusion suppressing layers formed inside the respective device regions to divide each of the device regions into an upper device region and a lower device region.

Abstract: In one embodiment, a semiconductor memory device includes a semiconductor substrate, and isolation layers formed in a surface of the semiconductor substrate, and separating the semiconductor substrate into active areas, the isolation layers and the active areas being alternately arranged along a predetermined direction parallel to the surface of the semiconductor substrate, a height of upper surfaces of the isolation layers being lower than a height of an upper surface of the semiconductor substrate. The device further includes diffusion layers formed on surfaces of the active areas, and a stress liner formed on upper surfaces and side surfaces of the diffusion layers, and formed of a material having a lattice constant smaller than a lattice constant of a material formed of the semiconductor substrate.

Abstract: A nonvolatile semiconductor memory device according to embodiment includes: a semiconductor substrate having an upper portion being partitioned into a plurality of semiconductor portions extending in a first direction; a charge storage film provided on the semiconductor portion; a word-line electrode provided on the semiconductor substrate and extending in a second direction intersecting with the first direction; and a pair of selection gate electrodes provided on both sides of the word-line electrode in the first direction on the semiconductor substrate and extending in the second direction, a shortest distance between a corner portion of each of the semiconductor portions and each of the selection gate electrodes being longer than a shortest distance between the corner portion of the semiconductor portion and the word-line electrode in a cross section parallel to the second direction.