Patents by Inventor Noboru Ryugo

Noboru Ryugo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4129090
    Abstract: In diffusing an impurity into semiconductor wafers within a silica tube by the use of a heating furnace, a method of diffusion involves the following steps: the semiconductor wafers are inserted into the tube from an inlet thereof, the inlet is sealed by a cap, the interior of the tube is placed under vacuum, and an atmosphere of the impurity is formed. Since, at heating, the tube is closed and no inert gas is fed thereinto, the temperature distribution within the tube is held uniform, and hence the quantities of impurity introduction into the semiconductor wafers are not varied.
    Type: Grant
    Filed: April 5, 1976
    Date of Patent: December 12, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Keizo Inaniwa, Noboru Ryugo
  • Patent number: 3948695
    Abstract: A method of diffusing an impurity into semiconductor wafers, wherein the semiconductor wafers and sources of the impurity are arranged in a pressure-reduced vessel or a vacuum vessel with their surfaces opposed, and the vessel is heated to deposit the impurity on the surfaces of the semiconductor wafers and to diffuse the impurity into the wafer surfaces in a separate open vessel, whereby the dispersion or variation of the surface impurity concentrations of the semiconductor wafers is lessened.
    Type: Grant
    Filed: February 7, 1974
    Date of Patent: April 6, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Noboru Ryugo, Keizo Inaniwa, Ichiro Takei
  • Patent number: 3948696
    Abstract: In diffusing an impurity into semiconductor wafers within a silica tube by the use of a heating furnace, a method of diffusion involves the following steps: the semiconductor wafers are inserted into the tube from an inlet thereof, the inlet is sealed by a cap, the interior of the tube is placed under vacuum, and an atmosphere of the impurity is formed. Since, at heating, the tube is closed and no inert gas is fed thereinto, the temperature distribution within the tube is held uniform, and hence the quantities of impurity introduction into the semiconductor wafers are not varied.
    Type: Grant
    Filed: February 28, 1974
    Date of Patent: April 6, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Keizo Inaniwa, Noboru Ryugo
  • Patent number: 3939017
    Abstract: A novel process for depositing and diffusing an impurity on and into the surface of a number of semiconductor wafers placed in parallel on a quartz boat. The impurity source is formed as a plurality of long and slender bars or a unitary tunnel-shaped element or a plurality of tunnel segments obtained by cutting the element apart. The impurity source as described above is mounted about the periphery of the semiconductor wafers arranged in a row on a quartz boat for reducing the consumption of the impurity source.
    Type: Grant
    Filed: March 29, 1974
    Date of Patent: February 17, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Noboru Ryugo, Keizo Inaniwa, Akira Sugiyama