Patents by Inventor Noboru Sugihara

Noboru Sugihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7904626
    Abstract: There is provided a technique which reduces an average processing time of low-priority accesses with suppressing an average delay increase of a high-priority access processing even in a case where high-priority access request and a low-request access request are simultaneously generated to a shared access processing unit and high-priority accesses are continuously generated. And, there is provided an access arbitration equipment comprising: an issued access request retention unit; a first interval determination circuit; and a second interval determination circuit. In a case where the first interval determination circuit determines that an interval is generated between an issued access processing and a most prior access processing and a second interval determination circuit determines that no interval is generated between the issued access processing and a second-prior access request, the priority order of the most prior access request and the second-prior access request is changed.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: March 8, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Teppei Hirotsu, Kotaro Shimamura, Teruaki Sakata, Noboru Sugihara
  • Publication number: 20090210588
    Abstract: A computation unit computes an elapse time until second data stored in a storage unit is outputted since first data is stored in the storage unit. An output request unit changes a speed at which an output unit outputs data based on the elapse time.
    Type: Application
    Filed: July 3, 2006
    Publication date: August 20, 2009
    Inventors: Makoto Adachi, Atsushi Nakao, Hiromichi Ito, Noboru Sugihara
  • Publication number: 20090024777
    Abstract: There is provided a technique which reduces an average processing time of low-priority accesses with suppressing an average delay increase of a high-priority access processing even in a case where high-priority access request and a low-request access request are simultaneously generated to a shared access processing unit and high-priority accesses are continuously generated. And, there is provided an access arbitration equipment comprising: an issued access request retention unit; a first interval determination circuit; and a second interval determination circuit. In a case where the first interval determination circuit determines that an interval is generated between an issued access processing and a most prior access processing and a second interval determination circuit determines that no interval is generated between the issued access processing and a second-prior access request, the priority order of the most prior access request and the second-prior access request is changed.
    Type: Application
    Filed: June 5, 2008
    Publication date: January 22, 2009
    Inventors: Teppei Hirotsu, Kotaro Shimamura, Teruaki Sakata, Noboru Sugihara
  • Publication number: 20070042159
    Abstract: A floor mat laid on a floor surface, constructed from a sheet-like or plate-like member with a predetermined thickness. The mat has relatively hard edge portions (4) at both ends in its width direction, and the edge portions (4) are formed as inclined surfaces gradually descending in a predetermined width to the outer edges of the mat. A belt-like central portion with a predetermined width is provided inside the edge portions (4), and the central portion is formed as an elastic portion that has a uniform thickness or height corresponding to the thickness of inner ends of the edge portions (4) and is softer in elasticity than the edge portions (4). In another example, the mat has a support mat (1) and a belt-like elastic mat (2). A receiving portion (3) is formed between the edge portions (4) of the support mat (1), in the front face side or back face side of the support mat. The elastic mat (2) is received in the receiving portion (3), serving as an elastic portion.
    Type: Application
    Filed: April 27, 2004
    Publication date: February 22, 2007
    Inventors: Minoru Sugihara, Noboru Sugihara
  • Publication number: 20050027921
    Abstract: A prefetch address calculation unit detects a branch instruction and a data access instruction to be reliably executed from a series of instruction included in an entry that is stored in a buffer at 1 cycle and outputs a prefetch request of its target address to a control unit. Then, decoding types of the series of instruction that is included in the entry, and setting it at an instruction type flag, the prefetch address calculation unit masks the output of the instruction type flag that has been executed by using an address signal of the instruction that is being executing presently and outputs a location of the instruction for issuing a prefetch request. By a signal from a control unit, the prefetch address calculation unit clears an instruction type flag corresponding to the instruction that issued the prefetch request.
    Type: Application
    Filed: May 11, 2004
    Publication date: February 3, 2005
    Inventors: Teppei Hirotsu, Kotaro Shimamura, Noboru Sugihara, Yasuhiro Nakatsuka, Teruaki Sakata