Abstract: A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).

Abstract: A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).

Abstract: A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).

Abstract: A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).

Abstract: A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).

Abstract: A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).

Abstract: A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).

Abstract: A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).

Abstract: A semiconductor integrated circuit having a plurality of fundamental cells respectively composed of a pair of p-channel field effect transistors and a pair of n-channel field effect transistors is disclosed. Elements of each fundamental cell are connected by lines, the fundamental cells are connected by lines, and a circuit is formed. The p-channel field effect transistors are formed in symmetry to each other, the n-channel field effect transistors are formed in symmetry to each other, one p-channel field effect transistor and one n-channel field effect transistor are formed in symmetry to each other, and the other p-channel field effect transistor and the other n-channel field effect transistor are formed in symmetry to each other.

Abstract: A semiconductor integrated circuit includes a semiconductor chip; an inner cell region; a plurality of input/output cell regions which are located around the inner cell region, and a plurality of pads which are provided between the plurality of input/output regions and sides of the semiconductor chip. Each unit area of the plurality of input/output cell regions is assigned to a corresponding input/output cell so as to be just sufficient for the corresponding input/output cell.

Abstract: A semiconductor integrated circuit having a plurality of fundamental cells respectively composed of a pair of p-channel field effect transistors and a pair of n-channel field effect transistors is disclosed. Elements of each fundamental cell are connected by lines, the fundamental cells are connected by lines, and a circuit is formed. The p-channel field effect transistors are formed in symmetry to each other, the n-channel field effect transistors are formed in symmetry to each other, one p-channel field effect transistor and one n-channel field effect transistor are formed in symmetry to each other, and the other p-channel field effect transistor and the other n-channel field effect transistor are formed in symmetry to each other.

Abstract: The present invention provides a level converting circuit comprising: a differential output transistor circuit for amplifying a difference between two mutually complementary input logic signals; a first output transistor circuit for outputting an inverted output logic signal based on a signal output by the differential output transistor circuit; and a second output transistor circuit for outputting an uninverted output logic signal based on a signal output by the differential output transistor circuit, wherein the first output transistor circuit further comprises first and second field-effect transistors and the second output transistor circuit further comprises third and fourth field-effect transistors. The differential output transistor circuit comprises a combination of first, second, third, fourth and fifth bais components which are each resistive element or a field-effect transistors.

Abstract: In a level conversion circuit for converting a pair of first-level signals into a pair of second-level signals, an input buffer circuit converts the pair of first-level signals into a pair of buffered signals which vary within a first voltage range situated below a second voltage range within which the pair of first-level signals vary. An amplifier circuit, which includes a plurality of CMOS differential amplifier circuits cascaded, converts the pair of buffered signals into the pair of second-level signals varying within a third voltage range broader than the second voltage range of the pair of first-level signals.

Abstract: A bipolar transistor, connected between a high voltage source and a low voltage source, has a base connected to an input terminal. A clamp circuit is connected between the high voltage source and the base of the transistor. A first resistor is connected in parallel with the clamp circuit. An output terminal is connected to the emitter of the bipolar transistor. In one embodiment, the clamp circuit is formed by two diodes connected in series. In another embodiment, a second resistor for limiting current is provided between the input terminal and the base of the transistor. In yet another embodiment, the resistance value of the first resistor is smaller than the ON resistance of a pMOS transistor in the output circuit of a CMOS circuit connected to the input terminal. A high level from the output terminal produces a high level ECL level output with a potential that depends on V.sub.BE of the bipolar transistor, while a low level output depends on the level of the clamp circuit.