Patents by Inventor Noboru YONEOKA

Noboru YONEOKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180157540
    Abstract: A control device includes, a semiconductor device including a processor and a programmable circuit, another programmable circuit coupled to the semiconductor device and another processor coupled to the semiconductor device and the other programmable circuit and configured to, when it is detected that power consumed by the semiconductor device exceeds a threshold value, specify a first task from among tasks each of which logic is programmed in the programmable circuit, a data transfer cost for the first task between the processor and the programmable circuit being smaller than each of data transfer costs for other tasks included in the tasks, program the logic of the first task into the other programmable circuit, and control the first task to be executed by the logic of the first task in the other programmable circuit.
    Type: Application
    Filed: November 21, 2017
    Publication date: June 7, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Noboru Yoneoka
  • Publication number: 20180046504
    Abstract: A control apparatus is communicably connected to a plurality of processing apparatuses, including a processor configured to determine whether the sum of an execution time of a first process, an execution time of a second process, and a time taken for a first processing apparatus among the plurality of processing apparatuses to rewrite a logic for executing the first process to a logic for executing the second process is equal to or smaller than a unit time; determine whether a data traffic between the plurality of processing apparatuses is equal to or smaller than a threshold when the first processing apparatus executes the first and second processes, and cause the first processing apparatus to execute the first and second processes when it is determined that the sum is equal to or smaller than the unit time and the data traffic is equal to or smaller than the threshold.
    Type: Application
    Filed: July 26, 2017
    Publication date: February 15, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Noboru YONEOKA
  • Publication number: 20160212427
    Abstract: A video encoding apparatus determines whether to substitute all quantized coefficients in a target coefficient group by zero, on the assumption that the subsequent coefficient groups include one or more quantized coefficients that are not zero, the target coefficient group being sequentially selected from the lowest-frequency among coefficient groups included in a block serving as a unit in orthogonal transform, and determines, for each coefficient group sequentially from the lowest-frequency coefficient group, whether to update, to a first quantized-coefficient candidate that is not zero and corresponding to the highest frequency in the coefficient group on the assumption that all the quantized coefficients in the subsequent coefficient groups are zero, a second quantized-coefficient candidate, which is already obtained, based on comparison between the first candidate and the second candidate in terms of a comparison cost obtained by subtracting a coding error related to the subsequent coefficient groups fro
    Type: Application
    Filed: January 20, 2016
    Publication date: July 21, 2016
    Applicant: FUJITSU LIMITED
    Inventor: NOBORU YONEOKA
  • Publication number: 20160044325
    Abstract: An image coding apparatus includes a coding and decoding unit configured to selectively encode and decode pictures to be used as a reference among a predetermined number of pictures based on information for discriminating between pictures to be used as a reference and pictures not to be used as a reference, followed by encoding pictures not to be used as a reference among the predetermined number of pictures, an in-loop filter configured to perform filtering with respect to the pictures decoded by the coding and decoding unit, and a control unit configured to suspend power supply to the in-loop filter in response to timing at which the coding and decoding unit encodes the pictures not to be used as a reference.
    Type: Application
    Filed: October 20, 2015
    Publication date: February 11, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Koji Kurihara, Kiyonori Morioka, Hidetoshi Matsumura, Noboru YONEOKA
  • Publication number: 20150350670
    Abstract: A coding apparatus includes identifying circuitry that identifies based on a count of frames coded referring to a reference frame among a series of frames, a count of vectors specifying search positions on the reference frame of a given frame when detection is performed for a motion vector of a block of the given frame to be coded among the series of frames; and determining circuitry that determines based on the member count and a maximum read data volume that can be read in of the reference frame per unit time, for a single given frame of the series of frames, a first maximum read data volume for a single given frame when image data is read in of a search range that includes a search position specified on the reference frame by a motion vector of a block on a reduced image obtained by reducing the given frame.
    Type: Application
    Filed: August 11, 2015
    Publication date: December 3, 2015
    Inventor: Noboru YONEOKA
  • Publication number: 20140362095
    Abstract: An image cache memory performs caching of image data, the image cache memory includes a cache buffer, a cache tag unit, a comparator, and a controller. The cache buffer stores cache data for each rectangular block including a plurality of pixels arranged in rectangle, and the cache tag unit stores tags each corresponding to a rectangular-block group including a plurality of rectangular blocks. The comparator makes comparison by using the tags stored in the cache tag unit, and the controller performs the caching by controlling the cache buffer, the cache tag unit, and the comparator.
    Type: Application
    Filed: April 23, 2014
    Publication date: December 11, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Noboru YONEOKA
  • Patent number: 8514947
    Abstract: A semiconductor device including a first processing unit processing an input signal based on a plurality of image compression standards, a signal generation unit outputting a switching signal to the first processing unit, a first calculation unit performing an operation on the input signal in accordance with a first coefficient that is based on the switching signal, a second calculation unit performing an operation on an output of the first calculation unit in accordance with a second coefficient that is based on the switching signal, a selection unit selecting one of the output of the first calculation unit and an output of the second calculation unit based on the switching signal, and a third calculation unit selecting one or both of the input signal and the output of the first calculation unit based on the switching signal and performing a predetermined calculation on the selected signal.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: August 20, 2013
    Assignee: Fujitsu Limited
    Inventors: Noboru Yoneoka, Hirofumi Nagaoka
  • Publication number: 20120195381
    Abstract: An image processing apparatus includes a subsampling circuit to generate a subsampled image based on a sampling position of each frame of an input image; a control circuit to assign a frame at a sampling position which is substantially the same as a sampling position of a frame to be encoded as a reference frame based on information of the sampling position of each frame and a structure of a group of pictures; and an encoder to encode the frame to be encoded by compressing the frame to be encoded using inter-frame prediction based on a subsampled image of the frame to be encoded and the reference frame.
    Type: Application
    Filed: January 27, 2012
    Publication date: August 2, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Yasuhiro WATANABE, Kiyonori Morioka, Noboru Yoneoka
  • Publication number: 20090172506
    Abstract: A semiconductor device including a first processing unit processing an input signal based on a plurality of image compression standards, a signal generation unit outputting a switching signal to the first processing unit, a first calculation unit performing an operation on the input signal in accordance with a first coefficient that is based on the switching signal, a second calculation unit performing an operation on an output of the first calculation unit in accordance with a second coefficient that is based on the switching signal, a selection unit selecting one of the output of the first calculation unit and an output of the second calculation unit based on the switching signal, and a third calculation unit selecting one or both of the input signal and the output of the first calculation unit based on the switching signal and performing a predetermined calculation on the selected signal.
    Type: Application
    Filed: December 24, 2008
    Publication date: July 2, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Noboru YONEOKA, Hirofumi Nagaoka