Patents by Inventor Nobu Izawa

Nobu Izawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5096081
    Abstract: A metal cover plate for covering a semiconductor chip mounted on a package base plate comprises an upper central portion, a flange extending outwardly from outer edges of the central portion, and a side wall portion extending perpendicularly from the flange along all sides thereof. The central portion has at least one portion in parallel with the package base plate. The central portion is formed with reinforcing portions in the form ridges of gable roofs and valleys in cross section, formed along diagonal lines of the central portion or in the form of a ridge or rib substantially semicircular in cross section extending upwardly or downwardly along each diagonal line. Deflection of the top wall portion of the package during pressure application is thus be minimized.
    Type: Grant
    Filed: February 22, 1989
    Date of Patent: March 17, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masamichi Shindo, Toshiharu Sakurai, Hideo Taguchi, Nobu Izawa
  • Patent number: 5025347
    Abstract: A semiconductor device of a type having a pin grid array, comprises a printed circuit board and a planar metal stem with a plurality of through holes. The stem is made of metal having a coefficient of thermal expansion .alpha.s. The printed circuit board has a predetermined wiring pattern on its upper surface and is made of a material having a maximum coefficient .alpha.p in the widthwise direction. The printed circuit board is superposed over the upper surface of the metal stem. A plurality of lead pins have upper portions inserted into the through holes of the stem and board and are in alignment with each other when the board and the stem are superposed one upon another. Connecting members connect the upper portions of the lead pins with their corresponding wiring patterns. In the semiconductor device, the absolute value .DELTA..alpha. of the difference between the maximum coefficient .alpha.p of the board and the coefficient .alpha.s of the stem (.DELTA..alpha.=.alpha.p -.alpha.
    Type: Grant
    Filed: April 11, 1989
    Date of Patent: June 18, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masamichi Shindo, Toshiharu Sakurai, Hideo Taguchi, Nobu Izawa