Patents by Inventor Nobuaki Ieda

Nobuaki Ieda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6229165
    Abstract: This invention provides a semiconductor device including a silicon layer, an insulating layer formed on the silicon layer, a first semiconductor device formed on the insulating film to convert light into an electric signal, and a second semiconductor device formed on the insulating film, wherein a silicon region is formed in the silicon layer to shield the second semiconductor device from light, and a through hole extending through the silicon layer except for the silicon region to input light to the first semiconductor device is formed in that portion of the silicon layer corresponding to the lower portions of the first and second semiconductor devices.
    Type: Grant
    Filed: August 28, 1998
    Date of Patent: May 8, 2001
    Assignee: NTT Electronics Corporation
    Inventors: Tetsushi Sakai, Nobuaki Ieda, Masayuki Ino, Shigeru Nakajima, Yukio Akazawa, Tsuneo Mano, Hiroshi Inokawa
  • Patent number: 4417163
    Abstract: The buffer circuit is provided with a high sensitivity balanced type flip-flop circuit and a capacative coupling provided by MOS capacitance, and a load drive circuit utilizes bootstrap effect, thus producing complementary signals having a MOS level from a TTL address input signal.
    Type: Grant
    Filed: February 17, 1981
    Date of Patent: November 22, 1983
    Assignees: Oki Electric Industry Co., Ltd., Nippon Telegraph and Telephone Public Corporation
    Inventors: Yoshio Otsuki, Masaru Uesugi, Nobuaki Ieda
  • Patent number: 4399372
    Abstract: Disclosed is a semiconductor integrated circuit device comprising a semiconductor chip including a plurality of elements constituting multi-functional circuits and a control signal generating circuit incorporated within the semiconductor chip. The control signal generating circuit includes a variable resistance element which irreversibly changes its resistivity when a voltage having a magnitude larger than a specific level, is applied. The variable resistance element is connected in series with a fixed resistor which is further connected in parallel to the output electrodes of a field effect transistor. A control signal is applied to the input terminal of the transistor when the resistance of the variable resistance element is intended to change. An output terminal connected to the connection of the serial connected elements indicates logical "1" or "0" depending on whether the variable resistance element is in the high resistivity state or low resistivity state.
    Type: Grant
    Filed: December 8, 1980
    Date of Patent: August 16, 1983
    Assignee: Nippon Telegraph and Telephone Public Corporation
    Inventors: Masafumi Tanimoto, Nobuaki Ieda, Masato Wada
  • Patent number: 4146902
    Abstract: A semiconductor switching element comprised by a high resistivity polycrystalline silicon resistor whose resistance irreversibly decreases to a small value at a threshold voltage upon the voltage across the resistor reaching the threshold voltage. A semiconductor memory device is constituted by using the switching element as a memory cell and a semiconductor gate element for controlling the current flowing through the semiconductor switching element.
    Type: Grant
    Filed: June 20, 1978
    Date of Patent: March 27, 1979
    Assignee: Nippon Telegraph and Telephone Public Corp.
    Inventors: Masafumi Tanimoto, Takashi Watanabe, Nobuaki Ieda, Junichi Murota
  • Patent number: 4070590
    Abstract: A weak signal detecting circuit in which a sensing circuit formed with a flip-flop circuit, and bit lines each having connected thereto a plurality of 1-transistor type memory cells, are interconnected by separation transistors for separating them from each other, and in which power supply transistors are inserted between power sources and the bit lines. When the power supply transistors are turned on, the separation transistors are turned off, so that a signal detection can be performed with little power consumption. Further, in such a case, the bit lines are disconnected from the sensing circuit to thereby enable a high-speed and highly sensitive detecting operation to be stably achieved regardless of the number of memory cells.
    Type: Grant
    Filed: August 9, 1976
    Date of Patent: January 24, 1978
    Assignee: Nippon Telegraph and Telephone Public Corporation
    Inventors: Nobuaki Ieda, Takao Yano