Patents by Inventor Nobuaki Ishiga
Nobuaki Ishiga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10716218Abstract: A display device is provided with a laminated wiring including a low-resistance conductive film, a low-reflection film mainly containing Al and functioning as a reflection preventing film, and a cap film which are sequentially laminated on a transparent substrate, and an insulting film formed so as to cover the laminated wiring.Type: GrantFiled: March 8, 2013Date of Patent: July 14, 2020Assignee: Mitsubishi Electric CorporationInventors: Masami Hayashi, Kenichi Miyamoto, Nobuaki Ishiga, Kensuke Nagayama, Naoki Tsumura
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Patent number: 10128270Abstract: The present disclosure relates to a method for manufacturing an active matrix substrate. A first laminated film in which a semiconductor film, a first transparent conductive film, and a first metal film are laminated is formed on a substrate. A photoresist pattern having a first part covering a formation area of a channel part of a thin film transistor, a second part covering a formation area of a pixel electrode, and a third part covering formation areas of a source electrode, a drain electrode, and a source line, is formed on the first laminated film. The first metal film, the first transparent conductive film, and the semiconductor film are patterned using the photoresist pattern; the first part is removed and the first metal film and the first transparent conductive film are patterned; and the second part is removed and the first metal film is patterned.Type: GrantFiled: November 17, 2016Date of Patent: November 13, 2018Assignee: Mitsubishi Electric CorporationInventors: Nobuaki Ishiga, Kazunori Inoue, Naoki Tsumura, Kensuke Nagayama, Yasuyoshi Ito
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Patent number: 9910199Abstract: A display includes: a laminated wiring with a conductive film arranged on a foundation layer, and a transparent film and a translucent film arranged on the conductive film; a wiring terminal part arranged at an edge portion of the laminated wiring and having the same laminated structure as that of the laminated wiring; and an insulating film that covers the laminated wiring and the wiring terminal part.Type: GrantFiled: August 19, 2016Date of Patent: March 6, 2018Assignee: Mitsubishi Electric CorporationInventors: Masami Hayashi, Kenichi Miyamoto, Nobuaki Ishiga, Naoki Tsumura, Kensuke Nagayama
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Patent number: 9673232Abstract: An oxide semiconductor film and an oxide conductive film are stacked to form a semiconductor layer. The oxide conductive film is made of a material by which the oxide conductive film is etched at a higher speed than the oxide semiconductor film for example with a PAN chemical containing phosphoric acid, nitric acid, and acetic acid. A source electrode and a drain electrode are electrically connected to the oxide semiconductor film through the oxide conductive film at least at an end portion of the source electrode and an end portion of the drain electrode facing each other. A channel region made of the oxide semiconductor film is formed between the source electrode and the drain electrode. The oxide semiconductor film has a substantially tapered shape in cross section at an end face thereof.Type: GrantFiled: June 8, 2015Date of Patent: June 6, 2017Assignee: Mitsubishi Electric CorporationInventors: Naoki Tsumura, Kensuke Nagayama, Nobuaki Ishiga, Kazunori Inoue
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Patent number: 9640557Abstract: A TFT array substrate has an organic insulating film formed of a photosensitive organic resin material. A common electrode and a lead-out wiring are formed on the organic insulating film, and a pixel electrode is formed above the common electrode with an interlayer insulating film provided between them. The pixel electrode is connected to the lead-out wiring through a contact hole formed in the interlayer insulating film. The lead-out wiring and the common electrode are connected to a drain electrode and a common wiring, respectively, through contact holes formed in the organic insulating film. A metal cap film is provided on each of the lead-out wiring and the common electrode in the contact holes formed in the organic insulating film.Type: GrantFiled: March 21, 2014Date of Patent: May 2, 2017Assignee: Mitsubishi Electric CorporationInventors: Koji Oda, Kazunori Inoue, Nobuaki Ishiga, Osamu Miyakawa
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Publication number: 20170069665Abstract: To reduce the number of photolithography processes in manufacturing an active matrix substrate. Provided is a TFT substrate which has a pixel electrode connected to a drain electrode of a TFT, a source line connected to a source electrode of the TFT, and a gate line connected to a gate electrode of the TFT. A source electrode, a drain electrode, and a source line include a conductive film of the same layer as the pixel electrode. Under the source line and the pixel electrode, there remains a semiconductor layer of the same layer as a semiconductor film which constitutes a channel part of the TFT substrate.Type: ApplicationFiled: November 17, 2016Publication date: March 9, 2017Applicant: Mitsubishi Electric CorporationInventors: Nobuaki ISHIGA, Kazunori INOUE, Naoki TSUMURA, Kensuke NAGAYAMA, Yasuyoshi ITO
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Publication number: 20160356933Abstract: A display includes: a laminated wiring with a conductive film arranged on a foundation layer, and a transparent film and a translucent film arranged on the conductive film; a wiring terminal part arranged at an edge portion of the laminated wiring and having the same laminated structure as that of the laminated wiring; and an insulating film that covers the laminated wiring and the wiring terminal part.Type: ApplicationFiled: August 19, 2016Publication date: December 8, 2016Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Masami HAYASHI, Kenichi MIYAMOTO, Nobuaki ISHIGA, Naoki TSUMURA, Kensuke NAGAYAMA
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Patent number: 9508750Abstract: A gate wiring, a source electrode, a source-electrode connecting wiring, a pixel electrode, a gate-terminal extraction electrode, and a source-terminal extraction electrode are formed in the same layer on a planarization insulating film. The gate wiring is connected to a gate electrode through a gate-electrode-portion contact hole. The source electrode is connected to a semiconductor film through a source-electrode-portion contact hole. The source-electrode connecting wiring is connected to the semiconductor film and a source wiring through the source-electrode-portion contact hole and a source-wiring-portion contact hole, respectively. The pixel electrode is connected to the semiconductor film through a drain (pixel)-electrode-portion contact hole.Type: GrantFiled: November 25, 2014Date of Patent: November 29, 2016Assignee: Mitsubishi Electric CorporationInventors: Kyosuke Hiwatashi, Kazunori Inoue, Kouji Oda, Nobuaki Ishiga, Kensuke Nagayama, Naoki Tsumura
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Patent number: 9461077Abstract: A thin film transistor includes: a semiconductor channel film; a gate insulating film on the semiconductor channel film; a gate electrode formed of a laminated film including a first conductive film and a second conductive film on the gate insulating film; an interlayer insulating film covering the semiconductor channel film, the gate insulating film, and the gate electrode; a source electrode formed of a laminated film including a third conductive film and a fourth conductive film formed on the interlayer insulating film; and a drain electrode formed of the third conductive film. A gate wiring is formed of the laminated film including the first conductive film and the second conductive film. A source wiring is formed of the laminated film including the third conductive film and the fourth conductive film. A pixel electrode is formed of the first conductive film. A counter electrode is formed of the third conductive film.Type: GrantFiled: August 31, 2015Date of Patent: October 4, 2016Assignee: Mitsubishi Electric CorporationInventors: Kazunori Inoue, Nobuaki Ishiga, Kensuke Nagayama, Naoki Tsumura
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Patent number: 9459380Abstract: A display includes: a laminated wiring with a conductive film arranged on a foundation layer, and a transparent film and a translucent film arranged on the conductive film; a wiring terminal part arranged at an edge portion of the laminated wiring and having the same laminated structure as that of the laminated wiring; and an insulating film that covers the laminated wiring and the wiring terminal part.Type: GrantFiled: December 4, 2015Date of Patent: October 4, 2016Assignee: Mitsubishi Electric CorporationInventors: Masami Hayashi, Kenichi Miyamoto, Nobuaki Ishiga, Naoki Tsumura, Kensuke Nagayama
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Patent number: 9343487Abstract: A TFT substrate includes a TFT including a source electrode having a lower source electrode and an upper source electrode, which are electrically connected to each other, and a drain electrode having a lower drain electrode and an upper drain electrode, which are electrically connected to each other. The lower source electrode and the lower drain electrode are in contact with a lower surface of the semiconductor film, and the upper source electrode and the upper drain electrode are in contact with an upper surface of the semiconductor film.Type: GrantFiled: August 28, 2015Date of Patent: May 17, 2016Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Kensuke Nagayama, Kazunori Inoue, Yasuyoshi Ito, Nobuaki Ishiga, Naoki Tsumura, Shinichi Yano
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Publication number: 20160084992Abstract: A display includes: a laminated wiring with a conductive film arranged on a foundation layer, and a transparent film and a translucent film arranged on the conductive film; a wiring terminal part arranged at an edge portion of the laminated wiring and having the same laminated structure as that of the laminated wiring; and an insulating film that covers the laminated wiring and the wiring terminal part.Type: ApplicationFiled: December 4, 2015Publication date: March 24, 2016Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Masami HAYASHI, Kenichi MIYAMOTO, Nobuaki ISHIGA, Naoki TSUMURA, Kensuke NAGAYAMA
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Patent number: 9250363Abstract: A display includes: a laminated wiring with a conductive film arranged on a foundation layer, and a transparent film and a translucent film arranged on the conductive film; a wiring terminal part arranged at an edge portion of the laminated wiring and having the same laminated structure as that of the laminated wiring; and an insulating film that covers the laminated wiring and the wiring terminal part.Type: GrantFiled: October 4, 2013Date of Patent: February 2, 2016Assignee: Mitsubishi Electric CorporationInventors: Masami Hayashi, Kenichi Miyamoto, Nobuaki Ishiga, Naoki Tsumura, Kensuke Nagayama
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Publication number: 20150372019Abstract: A thin film transistor includes: a semiconductor channel film; a gate insulating film on the semiconductor channel film; a gate electrode formed of a laminated film including a first conductive film and a second conductive film on the gate insulating film; an interlayer insulating film covering the semiconductor channel film, the gate insulating film, and the gate electrode; a source electrode formed of a laminated film including a third conductive film and a fourth conductive film formed on the interlayer insulating film; and a drain electrode formed of the third conductive film. A gate wiring is formed of the laminated film including the first conductive film and the second conductive film. A source wiring is formed of the laminated film including the third conductive film and the fourth conductive film. A pixel electrode is formed of the first conductive film. A counter electrode is formed of the third conductive film.Type: ApplicationFiled: August 31, 2015Publication date: December 24, 2015Applicant: Mitsubishi Electric CorporationInventors: Kazunori INOUE, Nobuaki ISHIGA, Kensuke NAGAYAMA, Naoki TSUMURA
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Publication number: 20150372027Abstract: A TFT substrate includes a TFT including a source electrode having a lower source electrode and an upper source electrode, which are electrically connected to each other, and a drain electrode having a lower drain electrode and an upper drain electrode, which are electrically connected to each other. The lower source electrode and the lower drain electrode are in contact with a lower surface of the semiconductor film, and the upper source electrode and the upper drain electrode are in contact with an upper surface of the semiconductor film.Type: ApplicationFiled: August 28, 2015Publication date: December 24, 2015Applicant: Mitsubishi Electric CorporationInventors: Kensuke NAGAYAMA, Kazunori INOUE, Yasuyoshi ITO, Nobuaki ISHIGA, Naoki TSUMURA, Shinichi YANO
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Publication number: 20150364503Abstract: An oxide semiconductor film and an oxide conductive film are stacked to form a semiconductor layer. The oxide conductive film is made of a material by which the oxide conductive film is etched at a higher speed than the oxide semiconductor film for example with a PAN chemical containing phosphoric acid, nitric acid, and acetic acid. A source electrode and a drain electrode are electrically connected to the oxide semiconductor film through the oxide conductive film at least at an end portion of the source electrode and an end portion of the drain electrode facing each other. A channel region made of the oxide semiconductor film is formed between the source electrode and the drain electrode. The oxide semiconductor film has a substantially tapered shape in cross section at an end face thereof.Type: ApplicationFiled: June 8, 2015Publication date: December 17, 2015Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Naoki TSUMURA, Kensuke NAGAYAMA, Nobuaki ISHIGA, Kazunori INOUE
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Patent number: 9209203Abstract: A thin film transistor includes: a semiconductor channel film; a gate insulating film on the semiconductor channel film; a gate electrode formed of a laminated film including a first conductive film and a second conductive film on the gate insulating film; an interlayer insulating film covering the semiconductor channel film, the gate insulating film, and the gate electrode; a source electrode formed of a laminated film including a third conductive film and a fourth conductive film formed on the interlayer insulating film; and a drain electrode formed of the third conductive film. A gate wiring is formed of the laminated film including the first conductive film and the second conductive film. A source wiring is formed of the laminated film including the third conductive film and the fourth conductive film. A pixel electrode is formed of the first conductive film. A counter electrode is formed of the third conductive film.Type: GrantFiled: December 3, 2014Date of Patent: December 8, 2015Assignee: Mitsubishi Electric CorporationInventors: Kazunori Inoue, Nobuaki Ishiga, Kensuke Nagayama, Naoki Tsumura
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Patent number: 9190420Abstract: A TFT substrate includes a TFT including a source electrode having a lower source electrode and an upper source electrode, which are electrically connected to each other, and a drain electrode having a lower drain electrode and an upper drain electrode, which are electrically connected to each other. The lower source electrode and the lower drain electrode are in contact with a lower surface of the semiconductor film, and the upper source electrode and the upper drain electrode are in contact with an upper surface of the semiconductor film.Type: GrantFiled: April 17, 2014Date of Patent: November 17, 2015Assignee: Mitsubishi Electric CorporationInventors: Kensuke Nagayama, Kazunori Inoue, Yasuyoshi Ito, Nobuaki Ishiga, Naoki Tsumura, Shinichi Yano
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Patent number: 9076875Abstract: A thin film transistor substrate includes a thin film transistor, a source wire, an upper-layer source wire, and a pixel electrode. The thin film transistor includes: a source electrode and a drain electrode located to be spaced from each other on the same plane; a semiconductor film located to straddle those electrodes; an insulating film located to cover at least the source electrode, the drain electrode, and the semiconductor film; an upper-layer source electrode and an upper-layer drain electrode located on the insulating film and respectively connected to the semiconductor film through contact holes; and a gate electrode located below or above the semiconductor film. The source wire extends from the source electrode. The upper-layer source wire extends from the upper-layer source electrode. The pixel electrode is electrically connected to the drain electrode.Type: GrantFiled: July 25, 2013Date of Patent: July 7, 2015Assignee: Mitsubishi Electric CorporationInventors: Kazunori Inoue, Nobuaki Ishiga, Kensuke Nagayama, Naoki Tsumura
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Publication number: 20150162358Abstract: A thin film transistor includes: a semiconductor channel film; a gate insulating film on the semiconductor channel film; a gate electrode formed of a laminated film including a first conductive film and a second conductive film on the gate insulating film; an interlayer insulating film covering the semiconductor channel film, the gate insulating film, and the gate electrode; a source electrode formed of a laminated film including a third conductive film and a fourth conductive film formed on the interlayer insulating film; and a drain electrode formed of the third conductive film. A gate wiring is formed of the laminated film including the first conductive film and the second conductive film. A source wiring is formed of the laminated film including the third conductive film and the fourth conductive film. A pixel electrode is formed of the first conductive film. A counter electrode is formed of the third conductive film.Type: ApplicationFiled: December 3, 2014Publication date: June 11, 2015Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kazunori INOUE, Nobuaki ISHIGA, Kensuke NAGAYAMA, Naoki TSUMURA