Patents by Inventor Nobuaki Izumi

Nobuaki Izumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8249147
    Abstract: The present invention is directed to an image decoding apparatus adapted for decoding information obtained by implementing inverse quantization and inverse orthogonal transform to image compressed information in which an input image signal is blocked to implement orthogonal transform thereto on the block basis so that quantization is performed with respect thereto, which comprises a reversible decoder (12) for decoding quantized and encoded transform coefficients, an inverse quantizer (13) indicating, as a flag, in inverse-quantizing transform coefficients which have been decoded by the reversible decoder (12), existence of each transform coefficient every processing block of inverse quantization, and an inverse transform element (14) for changing inverse transform processing to be implemented to inverse quantization transform coefficients within processing block by using the flag which has been indicated by the inverse-quantizer (13).
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: August 21, 2012
    Assignee: Sony Corporation
    Inventors: Shinji Watanabe, Nobuaki Izumi
  • Publication number: 20090285564
    Abstract: The present invention relates to a reproduction device, a reproduction method, and a program that enable the maintenance of real-time production of encoded video signals while suppressing a visually bad impression. As shown in FIG. 3, load reduction processes executed by a decoder include the following six types of processes: that is, a deblocking filter off process, a B picture simple motion compensation (MC) process, a P picture simple motion compensation (MC) process, a non-store picture frame skip process, a store picture frame skip process, and an only I picture reduction process. These six types of load reduction processes gradually reduce loads (that is, computation amounts) required for decoding by being added one at a time for execution in the described order. The present invention can apply to a decoder of an H.264/AVC, for example.
    Type: Application
    Filed: July 13, 2007
    Publication date: November 19, 2009
    Applicant: Sony Corporation
    Inventors: Tsuyoshi Kato, Jianming Li, Nobuaki Izumi
  • Patent number: 7593464
    Abstract: An inputted digital signal of a first format (DV video signal) is restored to a variable-length code by having its framing cancelled by a de-framing section 11, then decoded by a variable-length decoding (VLD) section 12, inversely quantized by an inverse quantizing (IQ) section 13, and inversely weighted by an inverse weighting (IW) section 14. Then, required resolution conversion in the orthogonal transform domain (frequency domain) is carried out on the inversely weighted video signal by a resolution converting section 16. After that, the video signal having the resolution converted is weighted by a weighting (W) section 18, then quantized by a quantizing (Q) section 19, coded by variable-length coding by a variable-length coding (VLC) section 20, and outputted as a digital signal of a second format (MPEG video signal).
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: September 22, 2009
    Assignee: Sony Corporation
    Inventors: Naofumi Yanagihara, Nobuaki Izumi
  • Patent number: 7526030
    Abstract: An inputted digital signal of a first format (DV video signal) is restored to a variable-length code by having its framing cancelled by a de-framing section 11, then decoded by a variable-length decoding (VLD) section 12, inversely quantized by an inverse quantizing (IQ) section 13, and inversely weighted by an inverse weighting (IW) section 14. Then, required resolution conversion in the orthogonal transform domain (frequency domain) is carried out on the inversely weighted video signal by a resolution converting section 16. After that, the video signal having the resolution converted is weighted by a weighting (W) section 18, then quantized by a quantizing (Q) section 19, coded by variable-length coding by a variable-length coding (VLC) section 20, and outputted as a digital signal of a second format (MPEG video signal).
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: April 28, 2009
    Assignee: Sony Corporation
    Inventors: Naofumi Yanagihara, Nobuaki Izumi
  • Publication number: 20070263728
    Abstract: An inputted digital signal of a first format (DV video signal) is restored to a variable-length code by having its framing cancelled by a de-framing section 11, then decoded by a variable-length decoding (VLD) section 12, inversely quantized by an inverse quantizing (IQ) section 13, and inversely weighted by an inverse weighting (IW) section 14. Then, required resolution conversion in the orthogonal transform domain (frequency domain) is carried out on the inversely weighted video signal by a resolution converting section 16. After that, the video signal having the resolution converted is weighted by a weighting (W) section 18, then quantized by a quantizing (Q) section 19, coded by variable-length coding by a variable-length coding (VLC) section 20, and outputted as a digital signal of a second format (MPEG video signal).
    Type: Application
    Filed: June 13, 2007
    Publication date: November 15, 2007
    Inventors: Naofumi Yanagihara, Nobuaki Izumi
  • Patent number: 7227898
    Abstract: An inputted digital signal of a first format (DV video signal) is restored to a variable-length code by having its framing cancelled by a de-framing section 11, then decoded by a variable-length decoding (VLD) section 12, inversely quantized by an inverse quantizing (IQ) section 13, and inversely weighted by an inverse weighting (IW) section 14. Then, required resolution conversion in the orthogonal transform domain (frequency domain) is carried out on the inversely weighted video signal by a resolution converting section 16. After that, the video signal having the resolution converted is weighted by a weighting (W) section 18, then quantized by a quantizing (Q) section 19, coded by variable-length coding by a variable-length coding (VLC) section 20, and outputted as a digital signal of a second format (MPEG video signal).
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: June 5, 2007
    Assignee: Sony Corporation
    Inventors: Naofumi Yanagihara, Nobuaki Izumi
  • Patent number: 7221709
    Abstract: An inputted digital signal of a first format (DV video signal) is restored to a variable-length code by having its framing cancelled by a de-framing section 11, then decoded by a variable-length decoding (VLD) section 12, inversely quantized by an inverse quantizing (IQ) section 13, and inversely weighted by an inverse weighting (IW) section 14. Then, required resolution conversion in the orthogonal transform domain (frequency domain) is carried out on the inversely weighted video signal by a resolution converting section 16. After that, the video signal having the resolution converted is weighted by a weighting (W) section 18, then quantized by a quantizing (Q) section 19, coded by variable-length coding by a variable-length coding (VLC) section 20, and outputted as a digital signal of a second format (MPEG video signal).
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: May 22, 2007
    Assignee: Sony Corporation
    Inventors: Naofumi Yanagihara, Nobuaki Izumi
  • Publication number: 20060291556
    Abstract: The present invention is directed to an image decoding apparatus adapted for decoding information obtained by implementing inverse quantization and inverse orthogonal transform to image compressed information in which an input image signal is blocked to implement orthogonal transform thereto on the block basis so that quantization is performed with respect thereto, which comprises a reversible decoder (12) for decoding quantized and encoded transform coefficients, an inverse quantizer (13) indicating, as a flag, in inverse-quantizing transform coefficients which have been decoded by the reversible decoder (12), existence of each transform coefficient every processing block of inverse quantization, and an inverse transform element (14) for changing inverse transform processing to be implemented to inverse quantization transform coefficients within processing block by using the flag which has been indicated by the inverse-quantizer (13).
    Type: Application
    Filed: November 30, 2004
    Publication date: December 28, 2006
    Inventors: Shinji Watanabe, Nobuaki Izumi
  • Patent number: 6963606
    Abstract: An input digital signal of a first format (DV video signal) is restored to a variable-length code by having its framing cancelled by a de-framing section 11, then decoded by a variable-length decoding (VLD) section 12, inversely quantized by an inverse quantizing (IQ) section 13, and inversely weighted by an inverse weighting (IW) section 14. Then required resolution conversion in the orthogonal transform domain (frequency domain) is carried out on the inversely weighted video signal by a resolution converting section 16. After that, the video signal having the resolution converted is weighted by a weighting (W) section 18, then quantized by a quantizing (Q) section 19, coded by a variable-length coding by a variable-length coding (VLC) section 20, and outputted as a digital signal of a second format (MPEG video signal).
    Type: Grant
    Filed: November 5, 1998
    Date of Patent: November 8, 2005
    Assignee: Sony Corporation
    Inventors: Naofumi Yanagihara, Nobuaki Izumi
  • Publication number: 20050175100
    Abstract: A data processing device able to generate prediction image data at short time even in the case of using a motion vector indicating outside an effective pixel region. A motion compensation circuit generates reference outside the effective pixel region and writes it into a memory based on reference image data inside the effective pixel region stored in the memory through decoding. A motion compensation circuit, in the case that the motion vector MV indicates outside the effective pixel region, generates prediction image data based on reference image data outside the effective pixel region stored in the memory.
    Type: Application
    Filed: February 2, 2005
    Publication date: August 11, 2005
    Inventors: Masahito Yamane, Nobuaki Izumi, Shinji Watanabe
  • Publication number: 20050157786
    Abstract: An inputted digital signal of a first format (DV video signal) is restored to a variable-length code by having its framing cancelled by a de-framing section 11, then decoded by a variable-length decoding (VLD) section 12, inversely quantized by an inverse quantizing (IQ) section 13, and inversely weighted by an inverse weighting (IW) section 14. Then, required resolution conversion in the orthogonal transform domain (frequency domain) is carried out on the inversely weighted video signal by a resolution converting section 16. After that, the video signal having the resolution converted is weighted by a weighting (W) section 18, then quantized by a quantizing (Q) section 19, coded by variable-length coding by a variable-length coding (VLC) section 20, and outputted as a digital signal of a second format (MPEG video signal).
    Type: Application
    Filed: March 16, 2005
    Publication date: July 21, 2005
    Inventors: Naofumi Yanagihara, Nobuaki Izumi
  • Publication number: 20050157787
    Abstract: An inputted digital signal of a first format (DV video signal) is restored to a variable-length code by having its framing cancelled by a de-framing section 11, then decoded by a variable-length decoding (VLD) section 12, inversely quantized by an inverse quantizing (IQ) section 13, and inversely weighted by an inverse weighting (IW) section 14. Then, required resolution conversion in the orthogonal transform domain (frequency domain) is carried out on the inversely weighted video signal by a resolution converting section 16. After that, the video signal having the resolution converted is weighted by a weighting (W) section 18, then quantized by a quantizing (Q) section 19, coded by variable-length coding by a variable-length coding (VLC) section 20, and outputted as a digital signal of a second format (MPEG video signal).
    Type: Application
    Filed: March 16, 2005
    Publication date: July 21, 2005
    Inventors: Naofumi Yanagihara, Nobuaki Izumi
  • Patent number: 6674897
    Abstract: A picture data compressing device has picture data divided by a blocking circuit 1 in to a plurality of blocks, each block consisting of a pre-set number of pixels and shuffled by a shuffling circuit 2. The blocked and shuffled data is transformed by a DCT circuit 3 into data in the frequency domain and re-quantized by a quantization circuit 4, thereby compressing the picture data. A red detector 6 determines whether a block from the shuffling circuit 2 is the red-based block. If the red detector 6 detects a red-based block, a controller 7 controls the quantization circuit 4 so that the quantization step of the quantization circuit 4 will become finer. Thus, the data of the red-based block susceptible to block distortion may be quantized with a finer quantization step for improving reproduction and alleviating block distortion.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: January 6, 2004
    Assignee: Sony Corporation
    Inventors: Kiminori Sugisaki, Jason Fischl, Nobuaki Izumi, Naofumi Yanagihara, Yuka Kiyama
  • Patent number: 6295086
    Abstract: To capture digital moving image information supplied from a digital VTR and to generate high quality still image data files, a programmable controller executes program instructions to determine whether an image capturing operation has been activated and to determine whether the extracted frame is valid/appropriate. If so, a header is appended, based on various video transmission standards such as NTSC or PAL, to the extracted frame data, thereby generating an image file. The frame data following this header is then recorded to the recording medium, such as a disk, for subsequent signal processing by the programmable controller.
    Type: Grant
    Filed: April 21, 1997
    Date of Patent: September 25, 2001
    Assignee: Sony Corporation
    Inventors: Shinichi Fukushima, Junichi Tsukamoto, Nobuaki Izumi
  • Patent number: 6157410
    Abstract: To display an image based on image file data generated from moving images, the number of pixels is changed in the horizontal or vertical direction of a display screen by a signal processing operation. Various television broadcast standards and display modes are supported. For example, in the NTSC system, a signal processing operation subjects frame data (720 by 480 pixels) to 8:9 pixel count conversion for converting the number of pixels in the horizontal direction from 720 to 640. An image based on the image file data (i.e., still picture) is therefore displayed on the computer screen with the correct aspect ratio.
    Type: Grant
    Filed: May 9, 1997
    Date of Patent: December 5, 2000
    Assignee: Sony Corporation
    Inventors: Nobuaki Izumi, Shinichi Fukushima, Junichi Tsukamoto
  • Patent number: 6078723
    Abstract: A recording/reproducing apparatus for reproducing recorded encoded picture data from a recording medium in varying speed without picture disruption. The recorded picture data are read from the recording medium and stored in a buffer memory. A detection circuit detects a picture header in the stored picture data and, depending upon the results of such detection, may or may not supply a clock signal therefrom. If a picture header is not detected, the detection circuit supplies the clock signal to the buffer memory and a delaying circuit. In response thereto, the stored picture data are read out from the buffer memory and supplied to the delaying circuit so as to be delayed by a predetermined amount prior to being supplied therefrom. If a picture header is detected during varying speed reproduction by the detection circuit, the clock signal is not supplied to the buffer memory and the delaying circuit, whereupon the delaying circuit outputs "0"s for a predetermined time period.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: June 20, 2000
    Assignee: Sony Corporation
    Inventors: Naofumi Yanagihara, Nobuaki Izumi
  • Patent number: 6061495
    Abstract: A recording/reproducing apparatus for reproducing recorded encoded picture data from a recording medium in varying speed without picture disruption. The recorded picture data are read from the recording medium and stored in a buffer memory. A detection circuit detects a picture header in the stored picture data and, depending upon the results of such detection, may or may not supply a clock signal therefrom. If a picture header is not detected, the detection circuit supplies the clock signal to the buffer memory and a delaying circuit. In response thereto, the stored picture data are read out from the buffer memory and supplied to the delaying circuit so as to be delayed by a predetermined amount prior to being supplied therefrom. If a picture header is detected during varying speed reproduction by the detection circuit, the clock signal is not supplied to the buffer memory and the delaying circuit, whereupon the delaying circuit outputs "0"s for a predetermined time period.
    Type: Grant
    Filed: July 11, 1997
    Date of Patent: May 9, 2000
    Assignee: Sony Corporation
    Inventors: Naofumi Yanagihara, Nobuaki Izumi
  • Patent number: 6040873
    Abstract: An apparatus and method for processing moving image data so as to obtain stationary image data representative of a desired image frame which is suitable for display on a display device. A moving portion of the image data corresponding to the desired image frame is detected and the image data corresponding to the detected moving portion is interpolated in accordance with a predetermined interpolation technique. A stationary image corresponding to the interpolated image data may be displayed on the display device with relatively high quality. The motion detection and field interpolation processing may eliminate or reduce stripes or the like which may otherwise be present in the displayed stationary image due to a deviation of the image data between the fields of the respective frame. Coefficients utilized for the motion detecting processing may be taken from previously stored values or may be set by an operator.
    Type: Grant
    Filed: May 14, 1997
    Date of Patent: March 21, 2000
    Assignee: Sony Corporation
    Inventors: Nobuaki Izumi, Shinichi Fukushima, Junichi Tsukamoto
  • Patent number: 5835664
    Abstract: A method and an apparatus for reproducing digital video signals in which every one-frame data of the digital video signals are recorded on n tracks of a recording medium by an inclined azimuth recording system are varying speed reproduced by a rotary head having n heads with a varying playback speed such that A=a(t.multidot.m.+-.1)/n, where a is a constant equal to 1 or 2 and m is a constant which is an integer other than 0. A picture corresponding to the digital video signals read out with the varying playback speed S is displayed on the screen. In this manner, non-continuous lines caused by temporal difference in neighboring macro-blocks during varying speed reproduction may be rendered less obtrusive for improving the picture quality of the varying speed reproduced picture.
    Type: Grant
    Filed: April 29, 1997
    Date of Patent: November 10, 1998
    Assignee: Sony Corporation
    Inventors: Yuka Oikawa, Naofumi Yanagihara, Nobuaki Izumi
  • Patent number: 5742728
    Abstract: A recording/reproducing apparatus for reproducing recorded encoded picture data from a recording medium in varying speed without picture disruption. The recorded picture data are read from the recording medium and stored in a buffer memory. A detection circuit detects a picture header in the stored picture data and, depending upon the results of such detection, may or may not supply a clock signal therefrom. If a picture header is not detected, the detection circuit supplies the clock signal to the buffer memory and a delaying circuit. In response thereto, the stored picture data are read out from the buffer memory and supplied to the delaying circuit so as to be delayed by a predetermined amount prior to being supplied therefrom. If a picture header is detected during varying speed reproduction by the detection circuit, the clock signal is not supplied to the buffer memory and the delaying circuit, whereupon the delaying circuit outputs "0"s for a predetermined time period.
    Type: Grant
    Filed: November 3, 1995
    Date of Patent: April 21, 1998
    Assignee: Sony Corporation
    Inventors: Naofumi Yanagihara, Nobuaki Izumi