Abstract: In a clock wiring of a semiconductor integrated circuit device or a printed wiring, a shield clock wiring to be connected with the same drive source as a drive source to be connected with the clock wiring is laid adjacent to the whole or partial length of the clock wiring.

Abstract: The collectors of differential pair transistors having their emitters connected to each other are connected to a positive power source voltage via respective load resistors. The emitters are connected to a negative power source voltage via a current source transistor.The base bias voltage of the current source transistor is supplied from a bias circuit operating on the difference voltage between the positive power source voltage and the negative power source voltage.When the positive power source voltage drops, the base bias voltage of the current source transistor drops in response thereto. Hence, the value of a current flowing through the current source transistor decreases. Due to this decrease of the current, the voltage drop of the load resistors decreases, thereby off-setting a low level potential of the collector output signals of the differential pair transistors.Thus, the differential pair transistors are prevented from being driven into saturation.

Abstract: A level conversion circuit for converting a signal of a polarity to a signal of the opposite polarity has differential pair transistors, push-pull type output transistors adapted to receive the differential outputs of opposite phases from the differential pair transistors, a plurality of protective transistors for protecting the output transistors and a capacitance separation element connected between the common collector outputs of the plurality of protective transistors and the output of one of the differential pair transistors. The protective transistor prevents both of the differential outputs from simultaneously taking high level due to various operating conditions of the conversion circuit. Therefore, the deterioration or breakdown of the output transistors caused by the through current is avoided. The capacitance separation element also contributes to prevent the reduction of operation speed of the differential transistors caused by the collector capacitances of the plurality of protective transistors.

Abstract: A memory circuit includes memory cells and access circuit for accessing to desired memory cells. The access circuit is driven by a driver which includes an emitter coupled logic for providing a switch-on signal of a low level in response to an input signal. A switch circuit in the driver provides the access circuit with a drive signal of a low level in response to the switch on signal. The driver further includes a control circuit for clamping the output of the emitter coupled logic to a non-drive signal of a high level when supply voltages does not satisfy predetermined conditions.