Abstract: A method for driving a semiconductor memory device includes a memory array having a plurality of memory cells arranged in rows and columns. Each memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a source and a drain as diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges. The method includes the steps of: selecting a row line connected to the gate electrode of a memory cell to be selected; grounding a first column line connected to the source of the memory cell to be selected; and applying a first potential to a second column line and a second potential to a third column line at the same time.

Abstract: A nonvolatile semiconductor memory device is provided comprising a plurality of memory cell arrays, each of which consists mainly of sidewall type memory cells arranged in a matrix, the memory cell having a MOSFET structure where memory functional element for holding charges are provided on both sides of a gate electrode. The memory cell array is divided into sectors. The memory device further comprises a sector selecting circuit for, when one of the memory cell arrays is to be erased collectively, sequentially selecting at most a predetermined number of the sectors at a time from the memory cell array to be erased, and an erase voltage applying circuit for, when the collective erasing action is carried out, applying a predetermined level of erasing voltage to the sectors selected at once by the sector selecting circuit.

Abstract: A nonvolatile semiconductor storage apparatus including: a first memory cell capable of storing a plurality of data values; a second memory cell capable of storing a plurality of data values; a resistance regulation section capable of regulating resistance, which regulates resistance such that a difference between a resistance value of a first connection line connected to the first memory cell and a resistance value of a second connection line connected to the second memory cell is reduced.

Abstract: A semiconductor memory device of the present invention includes an electrically programmable and erasable nonvolatile memory device which uses a plurality of memory cells requiring a first potential for reading data and a second potential for data programming, the second potential being higher than the first potential, a latch circuit for receiving data and temporarily storing the data, a pulse generator which generates a pulse used for programming data into a memory cell and is coupled in order to receive the second potential, a comparator for comparing data in the latch circuit with data in a memory cell, and a controller for controlling the pulse generator to repeatedly generate a pulse until the data in the latch circuit matches the data in the memory cell, the controller coupled to the comparator and the pulse generator. The controller controls so that the pulse is repeatedly generated until data is programmed in a memory cell.

Abstract: The present invention provides a method of programming, into a computer, a memory array having a plurality of memory cells, including a verification step 1 of verifying whether a memory cell has been already programmed or it has not been programmed yet per memory cell to be programmed, a flagging step 2 of flagging the memory cell in the case where it is verified that the memory cell has not been programmed yet in the several verifying steps, to which the memory cell is subjected thereafter, even if it is verified that the memory cell has been already programmed, a first application step 3 of applying a programming pulse having a programming level to the not-programmed memory cell without any flag, a repeat step 4 of repeating the verification step 1, the flagging step 2 and the first application step 3 until it is verified that all of the memory cells have been already programmed at least once, and a second application step 5 of applying a boost pulse having a boost programming level lower than that of the p

Abstract: The present invention provides a semiconductor memory device including a memory cell array in which a plurality of memory cells are arranged, a user interface circuit including a command queue having a logic circuit for accepting commands issued by an external user and generating a program memory address, and an array control circuit having a microcontroller and a program memory for storing therein an execution code, and executing an operation on the memory cell array, wherein the memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional elements formed on both sides of the gate electrode and having the function of retaining charges.

Abstract: A reading circuit of a memory cell includes a plurality of reference cells each having at least one of a plurality of possible states of the memory cell, a first pre-sense circuit for supplying current to the memory cell and outputting a first output voltage according to a storage state of the memory cell, a plurality of second pre-sense circuits for supplying currents to the plurality of reference cells and outputting second output voltages according to storage states of the reference cells, and a sense amplifier. The sense amplifier is constructed so that one of differential input stages of a differential amplifier is divided in parallel into the same number of pieces as that of the reference cells, the second output voltages of the plurality of second pre-sense circuits are supplied to the divided inputs, and the first output voltage of the first pre-sense circuit is supplied to the other differential input stage.

Abstract: A semiconductor storage device is provided, which comprises a memory array comprising memory elements, a write state machine for applying a first voltage for performing a write or erase operation, with respect to one of the memory elements, to the memory element via a bit line connected thereto, and thereafter, applying a second voltage for verifying whether or not the write or erase operation has been performed, to the memory element via the bit line, and a reset portion for grounding the bit line connected to the memory element after the write state machine has applied the first voltage and before the write state machine has applied the second voltage. Each memory element comprises a gate electrode, a channel region, diffusion regions, and memory function sections provided on opposite sides of the gate electrode and having a function of retaining charges.

Abstract: A semiconductor memory device includes a plurality of memory cells each capable of storing and programming N-level data; a reference cell storing a reference level used when reading a data level stored in the memory cells; a counter circuit counting number of times of reading of the reference cell; a check means for determining whether the reference level stored in the reference cell is within a preset range when the number of times of reading that is counted reaches a specified value; and a correction means for, if the check means determines that the reference level is out of the range, correcting the reference level to fall within the range in accordance with a master reference cell. With this constitution, it is possible to provide the semiconductor memory device capable of efficiently correcting the state of the reference cell, preventing the deterioration of the reference cell due to disturbance or the like, and highly accurately maintaining the level of the reference cell.

Abstract: The present invention provides a method of programming, into a computer, a memory array having a plurality of memory cells, including a verification step 1 of verifying whether a memory cell has been already programmed or it has not been programmed yet per memory cell to be programmed, a flagging step 2 of flagging the memory cell in the case where it is verified that the memory cell has not been programmed yet in the several verifying steps, to which the memory cell is subjected thereafter, even if it is verified that the memory cell has been already programmed, a first application step 3 of applying a programming pulse having a programming level to the not-programmed memory cell without any flag, a repeat step 4 of repeating the verification step 1, the flagging step 2 and the first application step 3 until it is verified that all of the memory cells have been already programmed at least once, and a second application step 5 of applying a boost pulse having a boost programming level lower than that of the p

Abstract: A method for driving a semiconductor memory device includes a memory array having a plurality of memory cells arranged in rows and columns. Each memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a source and a drain as diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges. The method includes the steps of: selecting a row line connected to the gate electrode of a memory cell to be selected; grounding a first column line connected to the source of the memory cell to be selected; and applying a first potential to a second column line and a second potential to a third column line at the same time.

Abstract: A semiconductor memory device of the present invention includes an electrically programmable and erasable nonvolatile memory device which uses a plurality of memory cells requiring a first potential for reading data and a second potential for data programming, the second potential being higher than the first potential, a latch circuit for receiving data and temporarily storing the data, a pulse generator which generates a pulse used for programming data into a memory cell and is coupled in order to receive the second potential, a comparator for comparing data in the latch circuit with data in a memory cell, and a controller for controlling the pulse generator to repeatedly generate a pulse until the data in the latch circuit matches the data in the memory cell, the controller coupled to the comparator and the pulse generator. The controller controls so that the pulse is repeatedly generated until data is programmed in a memory cell.

Abstract: A semiconductor memory device comprises a memory array in which memory cells having variable resistive elements (R11 to Rij) whose electrical resistance is varied by electrical stress and is held even after the electrical stress is released and selection transistors (T11 to Tij) comprising N type MOSFETs are arranged with a matrix; programming means for applying the electrical stress to the variable resistive elements (R11 to Rij) to program data into the memory cell; programming state detection means for detecting the variation in the electrical resistance at the time of the programming operation; and programming control means for stopping the application of the electrical stress when the electrical resistance is varied to a predetermined reference value. With this structure, it is possible to constitute the semiconductor memory device in which the time required for programming data is shortened and the programming precision is high.

Abstract: A semiconductor memory device includes a plurality of memory cells each capable of storing and programming N-level data; a reference cell storing a reference level used when reading a data level stored in the memory cells; a counter circuit counting number of times of reading of the reference cell; a check means for determining whether the reference level stored in the reference cell is within a preset range when the number of times of reading that is counted reaches a specified value; and a correction means for, if the check means determines that the reference level is out of the range, correcting the reference level to fall within the range in accordance with a master reference cell. With this constitution, it is possible to provide the semiconductor memory device capable of efficiently correcting the state of the reference cell, preventing the deterioration of the reference cell due to disturbance or the like, and highly accurately maintaining the level of the reference cell.

Abstract: A nonvolatile semiconductor storage apparatus comprises: a first memory cell capable of storing a plurality of data values; a second memory cell capable of storing a plurality of data values; a resistance regulation section capable of regulating resistance, which regulates resistance such that a difference between a resistance value of a first connection line connected to the first memory cell and a resistance value of a second connection line connected to the second memory cell is reduced.

Abstract: A raised voltage generation circuit includes a charge pump circuit for outputting a first voltage, a voltage dividing circuit for receiving the first voltage and outputting second and third voltages, a first transistor for receiving the second voltage at a gate thereof, a second transistor for receiving the third voltage at a gate thereof, and a control circuit for controlling whether or not to operate the charge pump circuit. Currents of the same value flow through the first and second transistors when the first voltage is equal to a predetermined value, currents of different values flow through the first and second transistors when the first voltage is not equal to the predetermined value, and the control circuit controls whether or not to operate the charge pump circuit based on the currents that flow through the first and second transistors.

Abstract: A raised voltage generation circuit includes a charge pump circuit for outputting a first voltage, a voltage dividing circuit for receiving the first voltage and outputting second and third voltages, a first transistor for receiving the second voltage at a gate thereof, a second transistor for receiving the third voltage at a gate thereof, and a control circuit for controlling whether or not to operate the charge pump circuit. Currents of the same value flow through the first and second transistors when the first voltage is equal to a predetermined value, currents of different values flow through the first and second transistors when the first voltage is not equal to the predetermined. value, and the control circuit controls whether or not to operate the charge pump circuit based on the currents that flow through the first and second transistors.