Abstract: This invention provides a micro controller in which a JTAG (Joint Test Action Group) port becomes available through a specific operation even after a security bit is set. More specifically, an embodiment of this invention provides a micro controller wherein: when an address signal AD2 and data DT2 are input from a JTAG port 11, the address signal AD2 and data DT2 are kept in shift registers 25 and 26 through a TAP (Test Access Port) 24; the address signal AD2 is forwarded to a flash ROM and data DT1 of the address specified by the address signal AD2 is read out and output a comparator 27; the data DT2 is also output the comparator 27; if the data DT1 and DT2 agree, the output signal from the comparator 27 turns “H” and the output signal from an AND gate 23 turns “L” independent of a security signal SEQ; and thereby a JTAG control circuit 12 is switched on and the JTAG port 11 becomes connected to TAPs 13 and 14 through the JTAG control circuit 12.

Abstract: A flash memory rewriting circuit capable of rewriting a flash ROM without Presenting any problem from the viewpoint of security of programs. In a transfer Program storing region of the flash ROM is stored a program to activate a CPU of a microcontroller and to transfer a rewriting data from external devices to peripherals. On a mask ROM is written, in a fixed manner, a program to activate a CPU and to write the rewriting data on a region other than the flash ROM. Because the program stored in the transfer program storing region is installed by users, no on except user can read or rewrite the program.

Abstract: In an electronic device system which includes integrated circuits, an amount of current which is passes through a resistive element located between a power supply voltage and an internal circuit of each integrated circuit is calculated on the basis of the power supply voltage and an voltage which occurs on an node between the resistive element and the internal circuit.

Abstract: This invention provides a micro controller in which JTAG port becomes available through a specific operation even after a security bit is set. More specifically, this invention provides a micro controller wherein: when an address signal AD2 and data DT2 are input from JTAG port 11, the address signal AD2 and data DT2 are kept in shift registers 25 and 26 through TAP 24; the address signal AD2 is forwarded to flash ROM and data DT1 of the address specified by the address signal AD2 is read out and output a comparator 27; the data DT2 is also output the comparator 27; when the data DT1 and DT2 agree, the output signal from the comparator 27 turns “H” and the output signal from the AND 23 turns “L” independent of security signal SEQ; and hereby the JTAG control circuit 12 turns switch-on and the JTAG port 11 becomes connected to the TAP 13 and 14 through the JTAG control circuit 12.

Abstract: An oscillation circuit includes an oscillation terminal, and an inverter which is coupled to the oscillation terminal and which outputs an oscillation signal according to a resonant frequency of a resonator to be connected to the oscillation terminal. The oscillation circuit also includes resistors having different resistance values, and a select circuit which sequentially operatively connects the resistors between the inverter and a voltage source in response to the oscillation signal.

Abstract: A frequency multiplication circuit generates an output clock signal having a frequency obtained by multiplying an external clock signal inputted from outside by a predetermined number.

Abstract: A typical structure for the data processing device of the present invention comprises a memory cell array part having a plurality of memory cells for storing data, first and second address terminals for receiving address signals, a first controller for receiving a first read signal and outputting a first read control signal, a second controller for receiving a second read signal and outputting a second read control signal, a first latch circuit for holding data outputted from a memory cell corresponding to an address signal provided at the first address terminal in response to the first read control signal and a second latch circuit for holding data outputted from a memory cell corresponding to the address signal provided at the second address terminal in response to the second read control signal.

Abstract: A structure for the data processing device, including a memory cell array part having a plurality of memory cells for storing data, first and second address terminals for receiving address signals, a first controller for receiving a first read signal and generating a first read control signal, a second controller for receiving a second read signal and generating a second read control signal, a first latch circuit for holding data provided by a memory cell corresponding to an address signal provided at the first address terminal in response to the first read control signal, and a second latch circuit for holding data provided by a memory cell corresponding to the address signal provided at the second address terminal in response to the second read control signal.