Abstract: A semiconductor device includes a first insulating film, a first wiring, a second insulating film, and a second wiring. The first insulating film is formed on a semiconductor substrate. The first wiring is formed on the first insulating film. The second insulating film is provided on the first insulating film to cover the first wiring. The second wiring is formed on the second insulating film. Furthermore, the second insulating film has a first opening part and a second opening part which expose the first wiring. The second wiring has a seed layer and a first plating layer. The first plating layer covers an entire side surface of the seed layer. The seed layer is not provided in the second opening part and a periphery thereof.

Abstract: A semiconductor device includes a first insulating film, a first wiring, a second insulating film, and a second wiring. The first insulating film is formed on a semiconductor substrate. The first wiring is formed on the first insulating film. The second insulating film is provided on the first insulating film to cover the first wiring. The second wiring is formed on the second insulating film. Furthermore, the second insulating film has a first opening part and a second opening part which expose the first wiring. The second wiring has a seed layer and a first plating layer. The first plating layer covers an entire side surface of the seed layer. The seed layer is not provided in the second opening part and a periphery thereof.

Abstract: A semiconductor device includes an insulating film formed on a semiconductor substrate, and a buried interconnect formed in the insulating film and made of copper or a copper alloy. A barrier metal layer made of a platinum group element or a platinum group element alloy is formed between the insulating film and the buried interconnect, and the barrier metal layer partially includes an amorphous structure having a degree of amorphousness that provides a relatively high barrier property.

Abstract: A lower barrier layer made of tantalum nitride having a thickness of approximately 25 nm is deposited by sputtering on a fourth insulating film inclusive of the sidewall surfaces and the bottom surfaces of a via hole and an upper-interconnect-forming groove. The sputtering is performed under the conditions where approximately 10 kW of DC source power is applied to a target. Thereafter, the DC source power is reduced to approximately 2 kW, and approximately 200 W of RF power is applied to a semiconductor substrate. Here, the lower barrier layer is subjected to a sputter-etching process employing argon gas at an etching amount of approximately 5 nm, so that a part of the lower barrier layer deposited on the bottom surface of the via hole is at least partially deposited on the lower part of the sidewall surface of the via hole.

Abstract: A lower barrier layer made of tantalum nitride having a thickness of approximately 25 nm is deposited by sputtering on a fourth insulating film inclusive of the sidewall surfaces and the bottom surfaces of a via hole and an upper-interconnect-forming groove. The sputtering is performed under the conditions where approximately 10 kW of DC source power is applied to a target. Thereafter, the DC source power is reduced to approximately 2 kW, and approximately 200 W of RF power is applied to a semiconductor substrate. Here, the lower barrier layer is subjected to a sputter-etching process employing argon gas at an etching amount of approximately 5 nm, so that a part of the lower barrier layer deposited on the bottom surface of the via hole is at least partially deposited on the lower part of the sidewall surface of the via hole.