Patents by Inventor Nobuaki Yamashita

Nobuaki Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11792917
    Abstract: An electronic module includes a first semiconductor device disposed on a first main surface of an insulating board of a printed wiring board, a first capacitor disposed on a second main surface of the insulating board at a position that overlaps with the first semiconductor device when viewed in a direction perpendicular to the first main surface, and a second capacitor disposed on the second main surface of the insulating board at a position that overlaps with the first semiconductor device when viewed in the direction perpendicular to the first main surface. A second electrode of the first capacitor is electrically connected to a ground pattern via a first ground via of the printed wiring board. A fourth electrode of the second capacitor is electrically connected to the ground pattern via a second ground via of the printed wiring board.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: October 17, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Takuya Kondo, Takashi Numagi, Nobuaki Yamashita
  • Publication number: 20230283890
    Abstract: An electric circuit includes a first power-supply line, a second power-supply line, a ground line, a first circuit, a second circuit, an RC series circuit, a capacitor, and a noise filter. The first circuit is configured to be electrically connected to the first power-supply line via a first power-supply terminal and electrically connected to the ground line via a first ground terminal. The second circuit is configured to be electrically connected to the second power-supply line via a second power-supply terminal and electrically connected to the ground line via a second ground terminal. The RC series circuit is disposed between the first power-supply terminal and the first ground terminal. The capacitor is disposed between the second power-supply terminal and the second ground terminal. The noise filter is disposed between the first power-supply line and the second power-supply line.
    Type: Application
    Filed: May 12, 2023
    Publication date: September 7, 2023
    Inventors: Nobuaki Yamashita, Takuya Kondo, Takashi Numagi
  • Patent number: 11689801
    Abstract: An electric circuit includes a first power-supply line, a second power-supply line, a ground line, a first circuit, a second circuit, an RC series circuit, a capacitor, and a noise filter. The first circuit is configured to be electrically connected to the first power-supply line via a first power-supply terminal and electrically connected to the ground line via a first ground terminal. The second circuit is configured to be electrically connected to the second power-supply line via a second power-supply terminal and electrically connected to the ground line via a second ground terminal. The RC series circuit is disposed between the first power-supply terminal and the first ground terminal. The capacitor is disposed between the second power-supply terminal and the second ground terminal. The noise filter is disposed between the first power-supply line and the second power-supply line.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: June 27, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Nobuaki Yamashita, Takuya Kondo, Takashi Numagi
  • Publication number: 20230187369
    Abstract: An electronic module includes a wiring board having a first main surface and a second main surface on a back side of the first main surface, and a first semiconductor element and a second semiconductor element that are mounted on the wiring board. The first semiconductor element includes a first signal terminal and a second signal terminal. The second semiconductor element includes a third signal terminal and a fourth signal terminal. The wiring board includes a first signal line including a first signal trace disposed in a first conductor layer, a second signal line including a second signal trace disposed in a second conductor layer that is closer to the second main surface than the first conductor layer is, a first ground trace disposed in the first conductor layer, and a second ground trace disposed in the second conductor layer.
    Type: Application
    Filed: November 29, 2022
    Publication date: June 15, 2023
    Inventors: Nobuaki Yamashita, Takashi Numagi, Kunihiko Uchida
  • Publication number: 20220321781
    Abstract: An electric circuit includes a first power-supply line, a second power-supply line, a ground line, a first circuit, a second circuit, an RC series circuit, a capacitor, and a noise filter. The first circuit is configured to be electrically connected to the first power-supply line via a first power-supply terminal and electrically connected to the ground line via a first ground terminal. The second circuit is configured to be electrically connected to the second power-supply line via a second power-supply terminal and electrically connected to the ground line via a second ground terminal. The RC series circuit is disposed between the first power-supply terminal and the first ground terminal. The capacitor is disposed between the second power-supply terminal and the second ground terminal. The noise filter is disposed between the first power-supply line and the second power-supply line.
    Type: Application
    Filed: March 24, 2022
    Publication date: October 6, 2022
    Inventors: Nobuaki Yamashita, Takuya Kondo, Takashi Numagi
  • Publication number: 20220304144
    Abstract: An electronic module includes a first semiconductor device disposed on a first main surface of an insulating board of a printed wiring board, a first capacitor disposed on a second main surface of the insulating board at a position that overlaps with the first semiconductor device when viewed in a direction perpendicular to the first main surface, and a second capacitor disposed on the second main surface of the insulating board at a position that overlaps with the first semiconductor device when viewed in the direction perpendicular to the first main surface. A second electrode of the first capacitor is electrically connected to a ground pattern via a first ground via of the printed wiring board. A fourth electrode of the second capacitor is electrically connected to the ground pattern via a second ground via of the printed wiring board.
    Type: Application
    Filed: March 14, 2022
    Publication date: September 22, 2022
    Inventors: Takuya Kondo, Takashi Numagi, Nobuaki Yamashita
  • Patent number: 9894751
    Abstract: First and second semiconductor devices and first and second bypass circuits are mounted on a printed wiring board. The first bypass circuit and the second bypass circuit are provided closer to the first semiconductor device and to the second semiconductor device, respectively. The first bypass circuit has one end connected to a power plane through a first power supply via and the other end connected to a ground plane through a first ground via. The second bypass circuit has one end connected to the power plane through a second power supply via and the other end connected to the ground plane through a second ground via. The ground plane has a slit between the connecting portions of the first and second ground vias to increase the impedance between the connecting portions of the first and the second ground vias. Thus, jitters caused by power supply noise can be reduced.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: February 13, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yusuke Murai, Shoji Matsumoto, Takashi Numagi, Hiroyuki Yamaguchi, Nobuaki Yamashita
  • Publication number: 20160157336
    Abstract: First and second semiconductor devices and first and second bypass circuits are mounted on a printed wiring board. The first bypass circuit and the second bypass circuit are provided closer to the first semiconductor device and to the second semiconductor device, respectively. The first bypass circuit has one end connected to a power plane through a first power supply via and the other end connected to a ground plane through a first ground via. The second bypass circuit has one end connected to the power plane through a second power supply via and the other end connected to the ground plane through a second ground via. The ground plane has a slit between the connecting portions of the first and second ground vias to increase the impedance between the connecting portions of the first and the second ground vias. Thus, jitters caused by power supply noise can be reduced.
    Type: Application
    Filed: November 18, 2015
    Publication date: June 2, 2016
    Inventors: Yusuke Murai, Shoji Matsumoto, Takashi Numagi, Hiroyuki Yamaguchi, Nobuaki Yamashita
  • Patent number: 9345126
    Abstract: A substrate of a semiconductor package comprises a conductor pattern which is formed in a surface layer, and is electrically connected to one terminal out of a power terminal and a ground terminal of a semiconductor element. The substrate also comprises in the surface layer a conductor pattern which is arranged while being separated from the conductor pattern, and a conductor pattern which is formed so as to have a wiring width thinner than that of the conductor pattern and connects the conductor pattern with the conductor pattern. The substrate also comprises a conductor pattern which is formed in an inner layer, faces the conductor pattern through a dielectric and is electrically connected to the other terminal out of the power terminal and the ground terminal of the semiconductor element.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: May 17, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Sou Hoshi, Nobuaki Yamashita, Yusuke Murai
  • Patent number: 9326370
    Abstract: Provided is a printed circuit board capable of increasing an inductance value of a power pattern and a ground pattern while keeping a low electric resistance value of the power pattern and the ground pattern. The printed circuit board includes a printed wiring board including: a power layer having a power pattern formed therein; and a ground layer having a ground pattern formed therein. On the printed wiring board, an LSI as a semiconductor device and an LSI as a power supply member are mounted. The ground pattern has a first ground region that overlaps the power pattern as viewed from the direction perpendicular to the surface of the printed wiring board. In the first ground region, at least one defect portion is formed. In the first ground region, the defect portion forms a region that is narrower than the power pattern.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: April 26, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yusuke Murai, Sou Hoshi, Nobuaki Yamashita
  • Patent number: 9084364
    Abstract: On a surface layer of a printed wiring board, main power supply patterns to be applied with different DC voltages are disposed in a second region. Power supply patterns are disposed on the surface layer, and the power supply patterns are led from the main power supply patterns to a first region. The power supply patterns connect power supply terminals of terminal groups in the second region. The power supply patterns connect the power supply terminals between the terminal groups in the first region. Power supply terminals of the terminal groups of a semiconductor package are electrically connected to the main power supply patterns by the power supply patterns. Thus, potential fluctuations are reduced and radiation noise is suppressed, and the number of layers of the printed wiring board is reduced.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: July 14, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Sou Hoshi, Nobuaki Yamashita, Yusuke Murai, Tohru Ohsaka
  • Publication number: 20140268586
    Abstract: A substrate of a semiconductor package comprises a conductor pattern which is formed in a surface layer, and is electrically connected to one terminal out of a power terminal and a ground terminal of a semiconductor element. The substrate also comprises in the surface layer a conductor pattern which is arranged while being separated from the conductor pattern, and a conductor pattern which is formed so as to have a wiring width thinner than that of the conductor pattern and connects the conductor pattern with the conductor pattern. The substrate also comprises a conductor pattern which is formed in an inner layer, faces the conductor pattern through a dielectric and is electrically connected to the other terminal out of the power terminal and the ground terminal of the semiconductor element.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 18, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Sou Hoshi, Nobuaki Yamashita, Yusuke Murai
  • Publication number: 20130343024
    Abstract: On a surface layer of a printed wiring board, main power supply patterns to be applied with different DC voltages are disposed in a second region. Power supply patterns are disposed on the surface layer, and the power supply patterns are led from the main power supply patterns to a first region. The power supply patterns connect power supply terminals of terminal groups in the second region. The power supply patterns connect the power supply terminals between the terminal groups in the first region. Power supply terminals of the terminal groups of a semiconductor package are electrically connected to the main power supply patterns by the power supply patterns. Thus, potential fluctuations are reduced and radiation noise is suppressed, and the number of layers of the printed wiring board is reduced.
    Type: Application
    Filed: June 12, 2013
    Publication date: December 26, 2013
    Inventors: Sou Hoshi, Nobuaki Yamashita, Yusuke Murai, Tohru Ohsaka
  • Publication number: 20130265726
    Abstract: Provided is a printed circuit board capable of increasing an inductance value of a power pattern and a ground pattern while keeping a low electric resistance value of the power pattern and the ground pattern. The printed circuit board includes a printed wiring board including: a power layer having a power pattern formed therein; and a ground layer having a ground pattern formed therein. On the printed wiring board, an LSI as a semiconductor device and an LSI as a power supply member are mounted. The ground pattern has a first ground region that overlaps the power pattern as viewed from the direction perpendicular to the surface of the printed wiring board. In the first ground region, at least one defect portion is formed. In the first ground region, the defect portion forms a region that is narrower than the power pattern.
    Type: Application
    Filed: March 28, 2013
    Publication date: October 10, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yusuke Murai, Sou Hoshi, Nobuaki Yamashita