Patents by Inventor Nobuaki Yamashita
Nobuaki Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12214988Abstract: A transport device includes a transport belt, an abutting unit, a moving mechanism, and a displacement detection unit. The transport belt has an adhesive layer capable of adhering to a medium, and is capable of transporting the medium adhering to the adhesive layer. The abutting unit is capable of abutting against a surface of the adhesive layer. It is assumed that a direction in which the abutting unit is away from the adhesive layer is a first direction and a direction opposite thereto is a second direction. The moving mechanism is capable of moving a position of the abutting unit with respect to the surface in the first direction and the second direction. The displacement detection unit detects a displacement amount of the transport belt in the first direction when the moving mechanism moves the abutting unit in the first direction while the abutting unit abuts against the surface.Type: GrantFiled: January 30, 2023Date of Patent: February 4, 2025Assignee: Seiko Epson CorporationInventors: Nobuaki Kamiyama, Takahiro Yamashita, Junpei Yamashita
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Patent number: 12219246Abstract: An electric circuit includes a first power-supply line, a second power-supply line, a ground line, a first circuit, a second circuit, an RC series circuit, a capacitor, and a noise filter. The first circuit is configured to be electrically connected to the first power-supply line via a first power-supply terminal and electrically connected to the ground line via a first ground terminal. The second circuit is configured to be electrically connected to the second power-supply line via a second power-supply terminal and electrically connected to the ground line via a second ground terminal. The RC series circuit is disposed between the first power-supply terminal and the first ground terminal. The capacitor is disposed between the second power-supply terminal and the second ground terminal. The noise filter is disposed between the first power-supply line and the second power-supply line.Type: GrantFiled: May 12, 2023Date of Patent: February 4, 2025Assignee: CANON KABUSHIKI KAISHAInventors: Nobuaki Yamashita, Takuya Kondo, Takashi Numagi
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Patent number: 12202273Abstract: A liquid ejecting device includes: a liquid ejecting head configured to eject a liquid from a plurality of nozzles to perform printing; an imaging unit configured to image a nozzle surface at which the plurality of nozzles are provided; an ejection-failure detecting unit configured to detect whether the plurality of nozzles have an ejection failure; a maintenance unit configured to perform maintenance of the liquid ejecting head; a notification unit configured to perform notification; and a control unit, in which, when the ejection-failure detecting unit detects the ejection failure, the control unit causes the imaging unit to image a nozzle for which the ejection failure is detected, infers a cause of the ejection failure based on a result of the imaging, and performs at least one of the maintenance and the notification based on the inferred cause.Type: GrantFiled: October 28, 2022Date of Patent: January 21, 2025Assignee: SEIKO EPSON CORPORATIONInventors: Nobuaki Kamiyama, Junpei Yamashita
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Publication number: 20240365464Abstract: A circuit board includes a wiring board, a first capacitor, a second capacitor, and a semiconductor device. The first capacitor and the second capacitor are stacked to each other on the wiring board. The semiconductor device is mounted on the wiring board. The first capacitor is provided between the second capacitor and the wiring board. A second capacitance of the second capacitor is larger than a first capacitance of the first capacitor.Type: ApplicationFiled: April 22, 2024Publication date: October 31, 2024Inventors: HIROYUKI YAMAGUCHI, NOBUAKI YAMASHITA, YOSHITOMO FUJISAWA
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Patent number: 11792917Abstract: An electronic module includes a first semiconductor device disposed on a first main surface of an insulating board of a printed wiring board, a first capacitor disposed on a second main surface of the insulating board at a position that overlaps with the first semiconductor device when viewed in a direction perpendicular to the first main surface, and a second capacitor disposed on the second main surface of the insulating board at a position that overlaps with the first semiconductor device when viewed in the direction perpendicular to the first main surface. A second electrode of the first capacitor is electrically connected to a ground pattern via a first ground via of the printed wiring board. A fourth electrode of the second capacitor is electrically connected to the ground pattern via a second ground via of the printed wiring board.Type: GrantFiled: March 14, 2022Date of Patent: October 17, 2023Assignee: CANON KABUSHIKI KAISHAInventors: Takuya Kondo, Takashi Numagi, Nobuaki Yamashita
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Publication number: 20230283890Abstract: An electric circuit includes a first power-supply line, a second power-supply line, a ground line, a first circuit, a second circuit, an RC series circuit, a capacitor, and a noise filter. The first circuit is configured to be electrically connected to the first power-supply line via a first power-supply terminal and electrically connected to the ground line via a first ground terminal. The second circuit is configured to be electrically connected to the second power-supply line via a second power-supply terminal and electrically connected to the ground line via a second ground terminal. The RC series circuit is disposed between the first power-supply terminal and the first ground terminal. The capacitor is disposed between the second power-supply terminal and the second ground terminal. The noise filter is disposed between the first power-supply line and the second power-supply line.Type: ApplicationFiled: May 12, 2023Publication date: September 7, 2023Inventors: Nobuaki Yamashita, Takuya Kondo, Takashi Numagi
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Patent number: 11689801Abstract: An electric circuit includes a first power-supply line, a second power-supply line, a ground line, a first circuit, a second circuit, an RC series circuit, a capacitor, and a noise filter. The first circuit is configured to be electrically connected to the first power-supply line via a first power-supply terminal and electrically connected to the ground line via a first ground terminal. The second circuit is configured to be electrically connected to the second power-supply line via a second power-supply terminal and electrically connected to the ground line via a second ground terminal. The RC series circuit is disposed between the first power-supply terminal and the first ground terminal. The capacitor is disposed between the second power-supply terminal and the second ground terminal. The noise filter is disposed between the first power-supply line and the second power-supply line.Type: GrantFiled: March 24, 2022Date of Patent: June 27, 2023Assignee: CANON KABUSHIKI KAISHAInventors: Nobuaki Yamashita, Takuya Kondo, Takashi Numagi
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Publication number: 20230187369Abstract: An electronic module includes a wiring board having a first main surface and a second main surface on a back side of the first main surface, and a first semiconductor element and a second semiconductor element that are mounted on the wiring board. The first semiconductor element includes a first signal terminal and a second signal terminal. The second semiconductor element includes a third signal terminal and a fourth signal terminal. The wiring board includes a first signal line including a first signal trace disposed in a first conductor layer, a second signal line including a second signal trace disposed in a second conductor layer that is closer to the second main surface than the first conductor layer is, a first ground trace disposed in the first conductor layer, and a second ground trace disposed in the second conductor layer.Type: ApplicationFiled: November 29, 2022Publication date: June 15, 2023Inventors: Nobuaki Yamashita, Takashi Numagi, Kunihiko Uchida
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Publication number: 20220321781Abstract: An electric circuit includes a first power-supply line, a second power-supply line, a ground line, a first circuit, a second circuit, an RC series circuit, a capacitor, and a noise filter. The first circuit is configured to be electrically connected to the first power-supply line via a first power-supply terminal and electrically connected to the ground line via a first ground terminal. The second circuit is configured to be electrically connected to the second power-supply line via a second power-supply terminal and electrically connected to the ground line via a second ground terminal. The RC series circuit is disposed between the first power-supply terminal and the first ground terminal. The capacitor is disposed between the second power-supply terminal and the second ground terminal. The noise filter is disposed between the first power-supply line and the second power-supply line.Type: ApplicationFiled: March 24, 2022Publication date: October 6, 2022Inventors: Nobuaki Yamashita, Takuya Kondo, Takashi Numagi
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Publication number: 20220304144Abstract: An electronic module includes a first semiconductor device disposed on a first main surface of an insulating board of a printed wiring board, a first capacitor disposed on a second main surface of the insulating board at a position that overlaps with the first semiconductor device when viewed in a direction perpendicular to the first main surface, and a second capacitor disposed on the second main surface of the insulating board at a position that overlaps with the first semiconductor device when viewed in the direction perpendicular to the first main surface. A second electrode of the first capacitor is electrically connected to a ground pattern via a first ground via of the printed wiring board. A fourth electrode of the second capacitor is electrically connected to the ground pattern via a second ground via of the printed wiring board.Type: ApplicationFiled: March 14, 2022Publication date: September 22, 2022Inventors: Takuya Kondo, Takashi Numagi, Nobuaki Yamashita
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Patent number: 9894751Abstract: First and second semiconductor devices and first and second bypass circuits are mounted on a printed wiring board. The first bypass circuit and the second bypass circuit are provided closer to the first semiconductor device and to the second semiconductor device, respectively. The first bypass circuit has one end connected to a power plane through a first power supply via and the other end connected to a ground plane through a first ground via. The second bypass circuit has one end connected to the power plane through a second power supply via and the other end connected to the ground plane through a second ground via. The ground plane has a slit between the connecting portions of the first and second ground vias to increase the impedance between the connecting portions of the first and the second ground vias. Thus, jitters caused by power supply noise can be reduced.Type: GrantFiled: November 18, 2015Date of Patent: February 13, 2018Assignee: Canon Kabushiki KaishaInventors: Yusuke Murai, Shoji Matsumoto, Takashi Numagi, Hiroyuki Yamaguchi, Nobuaki Yamashita
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Publication number: 20160157336Abstract: First and second semiconductor devices and first and second bypass circuits are mounted on a printed wiring board. The first bypass circuit and the second bypass circuit are provided closer to the first semiconductor device and to the second semiconductor device, respectively. The first bypass circuit has one end connected to a power plane through a first power supply via and the other end connected to a ground plane through a first ground via. The second bypass circuit has one end connected to the power plane through a second power supply via and the other end connected to the ground plane through a second ground via. The ground plane has a slit between the connecting portions of the first and second ground vias to increase the impedance between the connecting portions of the first and the second ground vias. Thus, jitters caused by power supply noise can be reduced.Type: ApplicationFiled: November 18, 2015Publication date: June 2, 2016Inventors: Yusuke Murai, Shoji Matsumoto, Takashi Numagi, Hiroyuki Yamaguchi, Nobuaki Yamashita
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Patent number: 9345126Abstract: A substrate of a semiconductor package comprises a conductor pattern which is formed in a surface layer, and is electrically connected to one terminal out of a power terminal and a ground terminal of a semiconductor element. The substrate also comprises in the surface layer a conductor pattern which is arranged while being separated from the conductor pattern, and a conductor pattern which is formed so as to have a wiring width thinner than that of the conductor pattern and connects the conductor pattern with the conductor pattern. The substrate also comprises a conductor pattern which is formed in an inner layer, faces the conductor pattern through a dielectric and is electrically connected to the other terminal out of the power terminal and the ground terminal of the semiconductor element.Type: GrantFiled: March 6, 2014Date of Patent: May 17, 2016Assignee: CANON KABUSHIKI KAISHAInventors: Sou Hoshi, Nobuaki Yamashita, Yusuke Murai
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Patent number: 9326370Abstract: Provided is a printed circuit board capable of increasing an inductance value of a power pattern and a ground pattern while keeping a low electric resistance value of the power pattern and the ground pattern. The printed circuit board includes a printed wiring board including: a power layer having a power pattern formed therein; and a ground layer having a ground pattern formed therein. On the printed wiring board, an LSI as a semiconductor device and an LSI as a power supply member are mounted. The ground pattern has a first ground region that overlaps the power pattern as viewed from the direction perpendicular to the surface of the printed wiring board. In the first ground region, at least one defect portion is formed. In the first ground region, the defect portion forms a region that is narrower than the power pattern.Type: GrantFiled: March 28, 2013Date of Patent: April 26, 2016Assignee: CANON KABUSHIKI KAISHAInventors: Yusuke Murai, Sou Hoshi, Nobuaki Yamashita
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Patent number: 9084364Abstract: On a surface layer of a printed wiring board, main power supply patterns to be applied with different DC voltages are disposed in a second region. Power supply patterns are disposed on the surface layer, and the power supply patterns are led from the main power supply patterns to a first region. The power supply patterns connect power supply terminals of terminal groups in the second region. The power supply patterns connect the power supply terminals between the terminal groups in the first region. Power supply terminals of the terminal groups of a semiconductor package are electrically connected to the main power supply patterns by the power supply patterns. Thus, potential fluctuations are reduced and radiation noise is suppressed, and the number of layers of the printed wiring board is reduced.Type: GrantFiled: June 12, 2013Date of Patent: July 14, 2015Assignee: CANON KABUSHIKI KAISHAInventors: Sou Hoshi, Nobuaki Yamashita, Yusuke Murai, Tohru Ohsaka
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Publication number: 20140268586Abstract: A substrate of a semiconductor package comprises a conductor pattern which is formed in a surface layer, and is electrically connected to one terminal out of a power terminal and a ground terminal of a semiconductor element. The substrate also comprises in the surface layer a conductor pattern which is arranged while being separated from the conductor pattern, and a conductor pattern which is formed so as to have a wiring width thinner than that of the conductor pattern and connects the conductor pattern with the conductor pattern. The substrate also comprises a conductor pattern which is formed in an inner layer, faces the conductor pattern through a dielectric and is electrically connected to the other terminal out of the power terminal and the ground terminal of the semiconductor element.Type: ApplicationFiled: March 6, 2014Publication date: September 18, 2014Applicant: CANON KABUSHIKI KAISHAInventors: Sou Hoshi, Nobuaki Yamashita, Yusuke Murai
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Publication number: 20130343024Abstract: On a surface layer of a printed wiring board, main power supply patterns to be applied with different DC voltages are disposed in a second region. Power supply patterns are disposed on the surface layer, and the power supply patterns are led from the main power supply patterns to a first region. The power supply patterns connect power supply terminals of terminal groups in the second region. The power supply patterns connect the power supply terminals between the terminal groups in the first region. Power supply terminals of the terminal groups of a semiconductor package are electrically connected to the main power supply patterns by the power supply patterns. Thus, potential fluctuations are reduced and radiation noise is suppressed, and the number of layers of the printed wiring board is reduced.Type: ApplicationFiled: June 12, 2013Publication date: December 26, 2013Inventors: Sou Hoshi, Nobuaki Yamashita, Yusuke Murai, Tohru Ohsaka
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Publication number: 20130265726Abstract: Provided is a printed circuit board capable of increasing an inductance value of a power pattern and a ground pattern while keeping a low electric resistance value of the power pattern and the ground pattern. The printed circuit board includes a printed wiring board including: a power layer having a power pattern formed therein; and a ground layer having a ground pattern formed therein. On the printed wiring board, an LSI as a semiconductor device and an LSI as a power supply member are mounted. The ground pattern has a first ground region that overlaps the power pattern as viewed from the direction perpendicular to the surface of the printed wiring board. In the first ground region, at least one defect portion is formed. In the first ground region, the defect portion forms a region that is narrower than the power pattern.Type: ApplicationFiled: March 28, 2013Publication date: October 10, 2013Applicant: CANON KABUSHIKI KAISHAInventors: Yusuke Murai, Sou Hoshi, Nobuaki Yamashita