Patents by Inventor Nobue Kosa

Nobue Kosa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7681173
    Abstract: In a mask data generation method, when auxiliary patterns are arranged with respect to a device pattern, an arrangement rule for a tip of the device pattern is designed to be different from that for other portions. For portions that are corrected to a large extent by an OPC process, such as the tip of the device pattern, an auxiliary pattern is spaced at an increased distance from the device pattern. Specifically, a distance at which an auxiliary pattern is spaced from the tip of the device pattern is set to be longer than a distance at which an auxiliary pattern is spaced from a long side of the device pattern.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: March 16, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Nobue Kosa, Tadao Yasuzato
  • Patent number: 7632614
    Abstract: A circuit pattern exposure method for irradiating illumination light onto a mask to transfer (offset) mask patterns that are formed in the mask to a semiconductor substrate, wherein the mask includes a plurality of main mask patterns that are arranged at a prescribed pitch and auxiliary mask patterns that are arranged outside the outermost main mask pattern and that are not to be transferred (offset) to the semiconductor substrate; the auxiliary mask patterns are provided with a first auxiliary mask row that is arranged adjacent to the outermost main mask pattern and a second auxiliary mask row that is arranged adjacent to the first auxiliary mask row; and the first auxiliary mask row and the second auxiliary mask row are arranged at a pitch that is narrower than the pitch of arrangement of the main mask patterns.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: December 15, 2009
    Assignee: Elpida Memory, Inc.
    Inventors: Nobue Kosa, Tadao Yasuzato
  • Publication number: 20070212620
    Abstract: In a mask data generation method, when auxiliary patterns are arranged with respect to a device pattern, an arrangement rule for a tip of the device pattern is designed to be different from that for other portions. For portions that are corrected to a large extent by an OPC process, such as the tip of the device pattern, an auxiliary pattern is spaced at an increased distance from the device pattern. Specifically, a distance at which an auxiliary pattern is spaced from the tip of the device pattern is set to be longer than a distance at which an auxiliary pattern is spaced from a long side of the device pattern.
    Type: Application
    Filed: March 8, 2007
    Publication date: September 13, 2007
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Nobue Kosa, Tadao Yasuzato
  • Publication number: 20070160918
    Abstract: A circuit pattern exposure method for irradiating illumination light onto a mask to transfer (offset) mask patterns that are formed in the mask to a semiconductor substrate, wherein the mask includes a plurality of main mask patterns that are arranged at a prescribed pitch and auxiliary mask patterns that are arranged outside the outermost main mask pattern and that are not to be transferred (offset) to the semiconductor substrate; the auxiliary mask patterns are provided with a first auxiliary mask row that is arranged adjacent to the outermost main mask pattern and a second auxiliary mask row that is arranged adjacent to the first auxiliary mask row; and the first auxiliary mask row and the second auxiliary mask row are arranged at a pitch that is narrower than the pitch of arrangement of the main mask patterns.
    Type: Application
    Filed: January 3, 2007
    Publication date: July 12, 2007
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Nobue Kosa, Tadao Yasuzato
  • Publication number: 20010018168
    Abstract: The resist development method of the present invention includes a step of applying a resist film to a wafer substrate, a step of exposing the resist film in a prescribed pattern, a step of removing the exposed part of the resist film with an alkaline liquid, and a step of cleaning the patterned resist film with ozone water.
    Type: Application
    Filed: February 21, 2001
    Publication date: August 30, 2001
    Applicant: NEC Corporation
    Inventors: Nobue Kosa, Yuji Shimizu