Abstract: This invention relates to a radio wave angle of incidence measurement apparatus which is applicable to radar and other detection systems, and which utilizes an antenna array with radiator elements distributed at a spacing larger than one half of the propagation wavelength. A radio signal is received by an antenna array that exhibit at least two different values of d/.lambda. (where d is the inter-element spacing of the radiator elements, .lambda. the propagation wavelength), and the resultant inter-element phase differences, of which there are at least two sets, are digitally measured. A phase difference converter circuit receives the digital signals representing the inter-element phase differences and processes them and generates an output signal that varies monotonically as the incident angle of the radio signal incident on the antenna array varies.

Abstract: An operation state display apparatus includes a counter for receiving input signals which respectively represent the individual operation states of a controlled object and for counting the duration time of at least one of the ON and OFF state of the input signal. A memory device is provided for memorizing the period of time lapse from an operation initiation reference time when the input signal goes from the OFF state to the ON state or vice versa. A display device is provided for displaying in the form of a time chart the operation state of the controlled object according to the data of the counter and of the memory device. The reference operation state of the controlled object can also be displayed on the display device.

Abstract: An operation state monitoring apparatus for monitoring an operation state of a controlled object is disclosed. The apparatus compares actual operation state data of the controlled object with reference operation state data of the controlled object read out from a reference operation state data memory and sets desirable data selected from the actual operation state data to the reference operation state data memory as the reference operation state data.

Abstract: An operation state display apparatus is disclosed having a first memory device for memorizing a time from an operation initiation reference time when an input signal is switched from the ON state to the OFF state or from the OFF state to the ON state wherein each input signal is for each operation state of a controlled object. A second memory device is provided for memorizing a last time of the OFF state or the ON state after switching from the ON state to the OFF state or from the OFF state to the ON state as the time from the operation initiation reference time. The apparatus includes a display device for displaying the operation state of the controlled object depending upon the data of the first and second memories in the form of a time chart.

Abstract: In a programmable logic controller in which the control sequence for a controlled-objective such as a machine tool is stored in a memory unit, and the controlled-objective is automatically operated in a predetermined sequence according to the control sequence stored in the memory unit; a display system is provided in which a sequence block obtained from the control sequence stored in the memory unit is displayed in the form of a sequence diagram, particularly, a sequence diagram which includes symbols of control elements such as relays. A necessary sequence block is automatically obtained from the control sequence and is displayed. This display system is capable of displaying the states of the control elements, such as the on-off states of relay contacts.

Abstract: A sequence control monitoring device is disclosed which receives from controlled-objects operated under a sequence control system signals independently representing the operating states of the individual controlled-objects. The monitoring device counts the time duration for which each input signal remains in its on or off state, compares the counted value with a preset value, and thus judges whether the operating state of the controlled-object is correct.

Abstract: A sequence controller of the digital logical circuit type, comprising a sequence program part and a processing circuit, wherein the desired sequence instruction is read from the sequence program part, and the sequence is processed and controlled by the processing circuit. A certain definite level is set at a branch point in an equivalent sequential circuit according to the path along which a signal of the sequential circuit is transmitted. This level and the on-off state of the branch point are stored in a memory. The given data are processed and controlled through the sequence program part and the memory.