Abstract: A multiprocessor system includes a plurality of processor units each transmitting an interrupt request signal indicating an interrupt request for which an interrupt-request destination processor unit is specified and receiving an interrupt signal and an interrupt control circuit receiving the interrupt request signal from each of the plurality of processor units and transmitting the interrupt signal to each of the plurality of processor units, wherein, the interrupt control circuit transmits the interrupt signal to the interrupt-request destination processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is not in a low power consumption state and transmits the interrupt signal to another processor unit different from the processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is in the low power consumption state.

Abstract: For the purpose of providing a simulation model allowing gate simulation but is capable of keeping the circuit information on the functional block (IP) secret, a method of generating a simulation model provided herein by the present invention comprises a step of generating a net list containing circuit information of an electronic circuit using a functional block; and a step of deleting the circuit information based on the net list, and generating a gate simulation model carrying out a timing simulation, including logic information and delay information between input/output of the functional block.

Abstract: A multiprocessor system includes a plurality of processor units each transmitting an interrupt request signal indicating an interrupt request for which an interrupt-request destination processor unit is specified and receiving an interrupt signal and an interrupt control circuit receiving the interrupt request signal from each of the plurality of processor units and transmitting the interrupt signal to each of the plurality of processor units, wherein, the interrupt control circuit transmits the interrupt signal to the interrupt-request destination processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is not in a low power consumption state and transmits the interrupt signal to another processor unit different from the processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is in the low power consumption state.

Abstract: A bus switch circuit having plural master side interface circuits inputting/outputting signals for plural bus masters respectively, and one or plural slave side interface circuit(s) inputting/outputting signals for one or plural bus slave(s), is provided. The master side interface circuit and the slave side interface circuit input an interrupt signal inputted at least to one bus master, and establish a signal path between the plural bus masters and the one or plural bus slave(s) in accordance with the interrupt signal.

Abstract: For the purpose of providing a simulation model allowing gate simulation but is capable of keeping the circuit information on the functional block (IP) secret, a method of generating a simulation model provided herein by the present invention comprises a step of generating a net list containing circuit information of an electronic circuit using a functional block; and a step of deleting the circuit information based on the net list, and generating a gate simulation model carrying out a timing simulation, including logic information and delay information between input/output of the functional block.

Abstract: A bus switch circuit having plural master side interface circuits inputting/outputting signals for plural bus masters respectively, and one or plural slave side interface circuit(s) inputting/outputting signals for one or plural bus slave(s), is provided. The master side interface circuit and the slave side interface circuit input an interrupt signal inputted at least to one bus master, and establish a signal path between the plural bus masters and the one or plural bus slave(s) in accordance with the interrupt signal.