Abstract: A delay time calculation unit calculates a delay time required to execute a computation path when an error countermeasure step is inserted into the computation path per computation path included in a scheduled CDFG file. An inserted graph selection unit selects a computation path for which the delay time does not exceed a target time as inserted graph. An error countermeasure insertion unit inserts an error countermeasure notation indicating the error countermeasure step into the inserted graph.

Abstract: Test information data includes a signal identifier and time period information which are being associated with a terminal identifier. An overlapping number counting part counts a first type overlapping number for each unit time period, based on the test information data. The first type overlapping number indicates the number of terminal identifiers being associated with time period information indicating an input time period which includes a unit time period and being associated with a first type signal identifier identifying a first type input signal. A determination circuit number decision part decides that the maximum overlapping number among the first type overlapping number of each unit time period is to be a first type determination circuit number. A design data generation part generates design data for a test circuit having the same number of first type determination circuits as the first type determination circuit number.