Abstract: A microcontroller is disposed on a receiving part of a wireless system in order to process a demodulation signal generated by a receiver circuit, and includes a memory and a CPU. The memory stores a control program of the microcontroller. The control program thereof includes a dual loop routine for an operation in reception standby mode. The dual loop routine has a first loop and a second loop included in the first loop. The CPU has an instruction set consisting of a plurality of instructions, and executes the instructions according to the program stored in the memory. The CPU executes an instruction irrelevant to an operation when the microcontroller is in reception mode during the second loop a number of times. The number of times is at least such that noise caused by the repetition of the second loop is lowered below a desired level.

Abstract: A peripheral circuit control register has a plurality of bits corresponding respectively to peripheral resources. A decoder activates an access signal to the peripheral resource at an access destination when the bit corresponding to the peripheral resource at the access destination in the peripheral circuit control register is under a set state in response to occurrence of access to any of the peripheral resources by a CPU. A functional specification of an evaluation chip can be made equivalent to those of product chips and development of a wrong user program can be prevented by setting in advance the bits of the peripheral circuit control register corresponding to the peripheral resources mounted to the product chip to the set state.

Abstract: An object is to provide a clock supply circuit capable of supplying a clock signal with a short oscillation stabilization waiting time. There is provided a clock supply circuit having a filter removing from a first clock signal pulses having a shorter pulse width than a threshold value and passing pulses having a longer pulse width than the threshold value to thereby output a second clock signal; and a divider dividing the second clock signal to thereby output a third clock signal.

Abstract: A microcontroller operating in synchronization with clock includes: an arithmetic unit operating in synchronization with the clock; an internal resource being connected to the arithmetic unit via a bus, and having at least a bus interface, and an internal circuit operating in synchronization with the clock; and a system resource prescaler which generates from the clock an operation permission signal denoting an operation permission state in m cycles out of n cycles of the clock (m=<n), and supplies the operation permission signal to the internal circuit of the internal resource. The above-mentioned internal circuit operates in synchronization with the clock when the operation permission signal denotes the operation permission state.

Abstract: The invention is a serial communication device for receiving serial data and sampling the serial data with synchronizing with communication clocks. The device has a clock generation unit for dividing a reference clock according to a predetermined dividing value, generating the communication clock each time the number of dividing value of the reference clock is generated, and generating a supplemental clock at any timing of the reference clock between adjacent communication clock; and a data decision circuit for receiving serial data, sampling 1-bit data at sampling timings including at least the adjacent communication clocks and the supplemental clock therebetween, and deciding the 1-bit data according to the decision by majority of the plurality of the sampling data which is sampled.

Abstract: A clock-signal generation device which changes an average frequency of a clock signal independently of a reference clock signal. A reference-clock-signal generation circuit generates a reference clock signal. A frequency-division circuit divides the frequency of the reference clock signal by using a natural number equal to or greater than one so as to generate a frequency-divided signal. A control circuit controls the frequency-division circuit so as to modify the frequency-divided signal by inserting extension cycles into the frequency-divided signal at predetermined intervals, and output the modified, frequency-divided signal as a clock signal. An output circuit outputs the clock signal generated by the control circuit. Therefore, the average frequency of the clock signal can be set arbitrarily and independently of the reference clock signal.

Abstract: An object is to provide a clock supply circuit capable of supplying a clock signal with a short oscillation stabilization waiting time. There is provided a clock supply circuit having a filter removing from a first clock signal pulses having a shorter pulse width than a threshold value and passing pulses having a longer pulse width than the threshold value to thereby output a second clock signal; and a divider dividing the second clock signal to thereby output a third clock signal.

Abstract: A processor includes an instruction buffer operable to store an opcode, an instruction decoder configured to keep one-to-one correspondences between opcodes and instructions, to identify an instruction corresponding to the opcode received from the instruction buffer based on the correspondences, and to output a signal indicative of the identified instruction, and a control circuit configured to perform an instruction operation in response to the signal output from the instruction decoder, wherein the instruction decoder is configured such that the correspondences are changeably set.

Abstract: A direct memory access device is provided which includes: a designation unit for designating transfer modes, when receiving an instruction to transfer data, to perform byte transfers or word transfers for first and last data of the data and word transfers for all other data; and a transfer unit for performing a data transfer by direct memory access from a data transfer source to a data transfer destination by the designated transfer modes.

Abstract: A microcontroller is disposed on a receiving part of a wireless system in order to process a demodulation signal generated by a receiver circuit, and includes a memory and a CPU. The memory stores a control program of the microcontroller. The control program thereof includes a dual loop routine for an operation in reception standby mode. The dual loop routine has a first loop and a second loop included in the first loop. The CPU has an instruction set consisting of a plurality of instructions, and executes the instructions according to the program stored in the memory. The CPU executes an instruction irrelevant to an operation when the microcontroller is in reception mode during the second loop a number of times. The number of times is at least such that noise caused by the repetition of the second loop is lowered below a desired level.

Abstract: A peripheral circuit control register has a plurality of bits corresponding respectively to peripheral resources. A decoder activates an access signal to the peripheral resource at an access destination when the bit corresponding to the peripheral resource at the access destination in the peripheral circuit control register is under a set state in response to occurrence of access to any of the peripheral resources by a CPU. A functional specification of an evaluation chip can be made equivalent to those of product chips and development of a wrong user program can be prevented by setting in advance the bits of the peripheral circuit control register corresponding to the peripheral resources mounted to the product chip to the set state.

Abstract: A direct memory access device is provided which includes: a designation unit for designating transfer modes, when receiving an instruction to transfer data, to perform byte transfers or word transfers for first and last data of the data and word transfers for all other data; and a transfer unit for performing a data transfer by direct memory access from a data transfer source to a data transfer destination by the designated transfer modes.

Abstract: The invention is a serial communication device for receiving serial data and sampling the serial data with synchronizing with communication clocks. The device has a clock generation unit for dividing a reference clock according to a predetermined dividing value, generating the communication clock each time the number of dividing value of the reference clock is generated, and generating a supplemental clock at any timing of the reference clock between adjacent communication clock; and a data decision circuit for receiving serial data, sampling 1-bit data at sampling timings including at least the adjacent communication clocks and the supplemental clock therebetween, and deciding the 1-bit data according to the decision by majority of the plurality of the sampling data which is sampled.

Abstract: A direct memory access device is provided which includes: a designation unit for designating transfer modes, when receiving an instruction to transfer data, to perform byte transfers or word transfers for first and last data of the data and word transfers for all other data; and a transfer unit for performing a data transfer by direct memory access from a data transfer source to a data transfer destination by the designated transfer modes.

Abstract: A microcontroller operating in synchronization with clock includes: an arithmetic unit operating in synchronization with the clock; an internal resource being connected to the arithmetic unit via a bus, and having at least a bus interface, and an internal circuit operating in synchronization with the clock; and a system resource prescaler which generates from the clock an operation permission signal denoting an operation permission state in m cycles out of n cycles of the clock (m=<n), and supplies the operation permission signal to the internal circuit of the internal resource. The above-mentioned internal circuit operates in synchronization with the clock when the operation permission signal denotes the operation permission state.

Abstract: A clock-signal generation device which changes an average frequency of a clock signal independently of a reference clock signal. A reference-clock-signal generation circuit generates a reference clock signal. A frequency-division circuit divides the frequency of the reference clock signal by using a natural number equal to or greater than one so as to generate a frequency-divided signal. A control circuit controls the frequency-division circuit so as to modify the frequency-divided signal by inserting extension cycles into the frequency-divided signal at predetermined intervals, and output the modified, frequency-divided signal as a clock signal. An output circuit outputs the clock signal generated by the control circuit. Therefore, the average frequency of the clock signal can be set arbitrarily and independently of the reference clock signal.

Abstract: A direct memory access device is provided which includes: a designation unit for designating transfer modes, when receiving an instruction to transfer data, to perform byte transfers or word transfers for first and last data of the data and word transfers for all other data; and a transfer unit for performing a data transfer by direct memory access from a data transfer source to a data transfer destination by the designated transfer modes.

Abstract: A microcomputer capable of efficiently accessing a plurality of devices with different access speeds through a shared bus. If, during access to a first device in compliance with a first access request, a second access request for a second device is issued from a CPU, an access completion time determination section determines the relation of order in time between the completion time of the access to the first device and the earliest time at which the access to the second device can be completed. If it is judged by the access completion time determination section that the access to the second device can be completed earlier than the completion time of the access to the first device, a bus access section accesses the second device in compliance with the second access request during the processing cycle of the access to the first device in compliance with the first access request.

Abstract: Disclosed is a scan path circuit for testing a logic circuit, which comprises a plurality of scan cells each having a scan in SI, a cell output and a clock input for receiving a clock signal, connected in series with respect to the scan ins and cell outputs. Each scan cell includes a scan flip-flop 21, and a selection circuit 31 which selects either a signal of a scan in SI or a signal of a scan out SO of the scan flip-flop 21 according on a selection controlling signal to provide the selected signal to the cell output. Determining the values of the selector controlling signal with a bypass controlling shift resister 45 permits forming a bypass between the scan data input terminal SDI and the scan in SI of any scan flip-flop except the first stage flip-flop, and/or a bypass between the scan data output terminal SDO and the scan out SO of any scan flip-flop except the final stage scan flip-flop.

Abstract: A method of communication between an adapter and a drive improves the data processing efficiency of the adapter and data transfer efficiency between the adapter and the drive. The drive has a slot to receive a disk cartridge containing a disk and drives the cartridge. The adapter is shaped to be inserted into the slot of the drive. The adapter has a controller to transfer data between the adapter and the drive through the heads thereof. The controller formats data so that the formatted data may fit into at least part of a disk format having tracks and sectors handled by the drive. The controller assigns a specific one of the tracks to the formatted data and transmits the track with the data to the drive.