Abstract: A semiconductor device having an SOI structure comprises an insular single crystal silicon body formed on an insulator layer, a first region of a first type semiconductor and source and drain regions of a second type semiconductor provided in the insular single crystal silicon body so that the first region is provided between the source and drain regions, a second region of the first type semiconductor in contact with the first region formed along a side of the source and drain regions, and a contact region of the first type semiconductor having an impurity density higher than those of the first and second regions formed in contact with the second region, so that a fixed voltage can be applied to the first region via the contact region.

Abstract: The packing density of a logic LSI based on standard cell methodology is increased by partially overlapping two adjoining cells so as to have common terminal regions to be connected to the wirings for supplying power. To this end, the pattern of the terminal region at a side edge of the cells in the row direction is standardized in its shape, size and position in each cell. The cells are registered in the cell library of a CAD system, together with a newly introduced additional symbol to indicate the region which may be overlapped during chip design operation using a display.