Patents by Inventor Nobuhiko Kenmochi
Nobuhiko Kenmochi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130002998Abstract: A polarizing element includes a plurality of polarizing sections, wherein a first polarizing section included in the plurality of polarizing sections has a first base material and a plurality of first acicular particles dispersed in the first base material such that long axes of the first acicular particles are aligned in substantially the same direction, a second polarizing section included in the plurality of polarizing sections has a second base material and a plurality of second acicular particles dispersed in the second base material such that long axes of the second acicular particles are aligned in substantially the same direction, and the specification of the first acicular particles is different from that of the second acicular particles.Type: ApplicationFiled: June 28, 2012Publication date: January 3, 2013Applicant: SEIKO EPSON CORPORATIONInventors: Daisuke SAWAKI, Nobuhiko KENMOCHI, Noriko Kenmochi
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Publication number: 20130003175Abstract: A screen includes a polarization layer having plural acicular particles provided with their major axes oriented nearly in the same direction on a substrate, and has polarization selectivity of reflecting light in one polarization direction and absorbing light in the other polarization direction of two polarization directions orthogonal to each other on a plane perpendicular to incident light.Type: ApplicationFiled: June 29, 2012Publication date: January 3, 2013Applicant: SEIKO EPSON CORPORATIONInventors: Nobuhiko KENMOCHI, Noriko Kenmochi
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Patent number: 8248697Abstract: A method for manufacturing an optical element that has a function to polarize and split incident light includes: a) forming a grid portion on a face of a substrate in a plural number with a predetermined pitch; b) forming a diffractive structure resist pattern on the face of the substrate; c) forming the diffractive structure by etching the substrate anisotropically in a thickness direction with the diffractive structure resist pattern; and d) forming a fine line on the grid portion by depositing a reflective material from an oblique direction onto the face of the substrate where the diffractive structure is provided.Type: GrantFiled: December 9, 2009Date of Patent: August 21, 2012Assignee: Seiko Epson CorporationInventor: Nobuhiko Kenmochi
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Patent number: 7961171Abstract: An electrooptic device having an image display period and an information gathering period includes a panel unit and a data processing unit. The panel unit includes a first substrate, a second substrate, an electrooptic material interposed between the first and second substrates, a plurality of first scan lines provided above the first substrate, a plurality of second scan lines provided above the first substrate and disposed in parallel to the first scan lines, a plurality of signal lines provided above the first substrate and intersecting the first scan lines and the second scan lines, and a plurality of pixels provided above the first substrate and disposed at intersections of the first scan lines and the second scan lines and signal lines. Each pixel located in an i-th row and a j-th column (i and j are both natural numbers) includes a first transistor, a second transistor, and a pixel electrode. The plurality of pixels are formed in a matrix on the first substrate.Type: GrantFiled: October 25, 2007Date of Patent: June 14, 2011Assignee: Seiko Epson CorporationInventors: Mitsutoshi Miyasaka, Nobuhiko Kenmochi
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Publication number: 20100182692Abstract: A method for manufacturing an optical element that has a function to polarize and split incident light includes: a) forming a grid portion on a face of a substrate in a plural number with a predetermined pitch; b) forming a diffractive structure resist pattern on the face of the substrate, the diffractive structure resist pattern corresponding to a diffractive structure that has a plurality of concave portions and a plurality of convex portions, the concave portions and the convex portions being arranged alternatively on the face of the substrate; c) forming the diffractive structure by etching the substrate anisotropically in a thickness direction with the diffractive structure resist pattern; and d) forming a fine line on the grid portion by depositing a reflective material from an oblique direction onto the face of the substrate where the diffractive structure is provided, the fine line being provided in a direction in which the grid portion extends.Type: ApplicationFiled: December 9, 2009Publication date: July 22, 2010Applicant: SEIKO EPSON CORPORATIONInventor: Nobuhiko KENMOCHI
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Patent number: 7755711Abstract: A liquid crystal device includes: a first scan line, a second scan line parallel to first scan line, a signal line intersecting the first scan line, a pixel arranged in a matrix; and a first light-shielding film. The pixel includes: a first transistor having a gate coupled to the first scan line, a source, and a drain, wherein either the source or drain is coupled to the signal line; a pixel electrode coupled to remaining source or drain of the first transistor; a common electrode disposed facing the pixel electrode; a liquid crystal layer disposed between the pixel electrode and common electrode; a second transistor having a gate coupled to the second scan line, wherein a source or drain of the second transistor is coupled to a source or drain of the first transistor, and the other source or drain is coupled to a power source line.Type: GrantFiled: December 13, 2007Date of Patent: July 13, 2010Assignee: Seiko Epson CorporationInventors: Nobuhiko Kenmochi, Mitsutoshi Miyasaka
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Publication number: 20090109377Abstract: An optical element includes: a substrate; a grid formed on the substrate, the grid including a plurality of micro-wires and having a polarization-separation function; and a diffraction function layer formed above the grid. In the element, the diffraction function layer has at least two kinds of regions in a plane, and at least the two kinds of regions have different refractive indexes.Type: ApplicationFiled: October 13, 2008Publication date: April 30, 2009Applicant: SEIKO EPSON CORPORATIONInventors: Daisuke SAWAKI, Nobuhiko KENMOCHI
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Publication number: 20080158461Abstract: A liquid crystal device includes: a first scan line, a second scan line parallel to first scan line, a signal line intersecting the first scan line, a pixel arranged in a matrix; and a first light-shielding film. The pixel includes: a first transistor having a gate coupled to the first scan line, a source, and a drain, wherein either the source or drain is coupled to the signal line; a pixel electrode coupled to remaining source or drain of the first transistor; a common electrode disposed facing the pixel electrode; a liquid crystal layer disposed between the pixel electrode and common electrode; a second transistor having a gate coupled to the second scan line, wherein a source or drain of the second transistor is coupled to a source or drain of the first transistor, and the other source or drain is coupled to a power source line.Type: ApplicationFiled: December 13, 2007Publication date: July 3, 2008Applicant: SEIKO EPSON CORPORATIONInventors: Nobuhiko KENMOCHI, Mitsutoshi MIYASAKA
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Publication number: 20080100566Abstract: An electrooptic device having an image display period and an information gathering period includes a panel unit and a data processing unit. The panel unit includes a first substrate, a second substrate, an electrooptic material interposed between the first and second substrates, a plurality of first scan lines provided above the first substrate, a plurality of second scan lines provided above the first substrate and disposed in parallel to the first scan lines, a plurality of signal lines provided above the first substrate and intersecting the first scan lines and the second scan lines, and a plurality of pixels provided above the first substrate and disposed at intersections of the first scan lines and the second scan lines and signal lines. Each pixel located in an i-th row and a j-th column (i and j are both natural numbers) includes a first transistor, a second transistor, and a pixel electrode. The plurality of pixels are formed in a matrix on the first substrate.Type: ApplicationFiled: October 25, 2007Publication date: May 1, 2008Applicant: Seiko Epson CorporationInventors: Mitsutoshi Miyasaka, Nobuhiko Kenmochi
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Patent number: 7061975Abstract: In accordance with the invention, in a nonrecursive digital filter, the number of times each bit of input data passes through a shift register is reduced to save power. Despreading data is sent to a first shift register and a second shift register, each having a number of stages obtained by dividing the usual number of stages by two, and both shift registers alternately perform a shift operation at both edges of a shift clock. Multiplexers are provided for selecting the odd-numbered codes of reference codes stored in a reference-code register when the shift clock is in an OFF state and for selecting the even-numbered codes when the shift clock is in an ON state, and multiplexers are provided that perform the selections analogous to the above.Type: GrantFiled: December 18, 2000Date of Patent: June 13, 2006Assignee: Seiko Epson CorporationInventor: Nobuhiko Kenmochi
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Patent number: 6587452Abstract: A mapping memory, for use with a transmitter, for mapping a first signal segment and a second signal segment of a packet so that each signal segment has the same average power level. Each signal segment is characterized by a different modulation format. The first signal segment might use BPSK, while the second signal segment might use QAM, having multiple amplitude levels.Type: GrantFiled: January 4, 1999Date of Patent: July 1, 2003Assignees: Golden Bridge Technology, Inc., Seiko Epson CorporationInventors: Sorin Davidovici, Emmanuel Kanterakis, Izumi Iida, Norio Hama, Nobuhiko Kenmochi
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Publication number: 20030091121Abstract: To provide a multi-valued FSK communication method and a multi-valued FSK communication apparatus having a simplified circuit configuration for receiving a multi-valued FSK packet. A transmitter side transmits a packet including a synchronization signal part using the maximum value and the minimum value of multi-valued FSK and a payload part using all values of multi-valued FSK. A receiver side receives the packet, and a reception circuit 3 forms an analog demodulation signal Sda by demodulating a reception signal and a binary signal Sb by binarizing the analog demodulation signal Sdm. These signals Sda and Sb are supplied to a received data processing unit 23 of a baseband signal processor 12. The received data processing unit 23 establishes synchronization based on the binary signal Sb.Type: ApplicationFiled: November 13, 2002Publication date: May 15, 2003Applicant: Seiko Epson CorporationInventor: Nobuhiko Kenmochi
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Publication number: 20020159515Abstract: In a nonrecursive digital filter, the number of times each bit of input data passes through a shift register is reduced to save power.Type: ApplicationFiled: August 16, 2001Publication date: October 31, 2002Inventor: Nobuhiko Kenmochi
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Patent number: 6212244Abstract: A two-step automatic-gain-control (AGC) loop for use with a receiver. An AGC amplifier amplifies a received signal. From an output signal from the AGC amplifier, a received-signal-strength-indicator (RSSI) circuit generates an RSSI signal proportional to a received-signal-power level of the received signal. An RSSI-mapping circuit has an RSSI-mapping table. From the RSSI signal, the RSSI-mapping circuit, using the RSSI-mapping table, generates an AGC signal. An AGC-storing circuit stores the AGC signal. The AGC amplifier uses the stored-AGC signal to adjust the AGC gain. A converter circuit converts the output signal from the AGC amplifier to an in-phase component and a quadrature-phase component at a processing frequency. The error circuit determines an error signal from the in-phase component and the quadrature-phase component.Type: GrantFiled: January 9, 1998Date of Patent: April 3, 2001Assignees: Golden Bridge Technology, Inc., Seiko Epson Corp.Inventors: Sorin Davidovici, Emmanuel Kanterakis, Izumi Iida, Norio Hama, Nobuhiko Kenmochi