Abstract: In a router unit (20) for use in supplying an input packet (PI) from an input port (I) to an output port (O) with reference to a destination bit series included in the input packet, each input buffer (22) divides the destination bit series into a plurality of partial bit series specified by series positions. A predetermined one of the series positions is assigned to the router unit and is represented by a position signal (PS) to select the partial bit series from the predetermined series position. An output buffer (46) is determined in consideration of the selected partial bit series and is loaded with the input packet. The input packet is sent from the output buffer to the output port as an output packet (PO) to protect the input packet from conflicting with another input packet at the output port. A plurality of the router units may be included in a plurality of stages each of which is given the position signal different from that of the other stages.

Abstract: A majority decision circuit is disclosed having reduced shift register bit capacity and the capability of providing a majority decision for varying repetition number. A full adder is used and the data words are applied serially to the carry input. The output is applied via shift registers back to the input, and a bias value is applied to the second input. The carry-out bits of the adder represent the majority decision.