Patents by Inventor Nobuhiko Kurata

Nobuhiko Kurata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE COMPRISING DIFFERENT LEVEL INTERCONNECTION LAYERS CONNECTED BY CONDUCTOR LAYERS INCLUDING CONDUCTOR LAYER FOR REDUNDANCY
    Publication number: 20110309522
    Abstract: A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for redundancy is disposed by the side of the regular via plug and between the regular via plug and the third interconnection layer. An extended portion of the second interconnection layer is extended from a portion connected to the via plug for redundancy on the second interconnection layer toward the third interconnection layer. The extended portion has a dimension smaller than the minimum dimension prescribed in the interconnection line design rule.
    Type: Application
    Filed: August 29, 2011
    Publication date: December 22, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuhiko Kurata, Kouichirou Inoue, Shinji Fujii, Muneaki Maeno
  • Semiconductor integrated circuit device comprising different level interconnection layers connected by conductor layers including conductor layer for redundancy
    Patent number: 8030773
    Abstract: A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for redundancy is disposed by the side of the regular via plug and between the regular via plug and the third interconnection layer. An extended portion of the second interconnection layer is extended from a portion connected to the via plug for redundancy on the second interconnection layer toward the third interconnection layer. The extended portion has a dimension smaller than the minimum dimension prescribed in the interconnection line design rule.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: October 4, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhiko Kurata, Kouichirou Inoue, Shinji Fujii, Muneaki Maeno
  • SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE COMPRISING DIFFERENT LEVEL INTERCONNECTION LAYERS CONNECTED BY CONDUCTOR LAYERS INCLUDING CONDUCTOR LAYER FOR REDUNDANCY
    Publication number: 20070273028
    Abstract: A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for redundancy is disposed by the side of the regular via plug and between the regular via plug and the third interconnection layer. An extended portion of the second interconnection layer is extended from a portion connected to the via plug for redundancy on the second interconnection layer toward the third interconnection layer. The extended portion has a dimension smaller than the minimum dimension prescribed in the interconnection line design rule.
    Type: Application
    Filed: May 24, 2007
    Publication date: November 29, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuhiko Kurata, Kouichirou Inoue, Shinji Fujii, Muneaki Maeno