Patents by Inventor Nobuhiko Ohno

Nobuhiko Ohno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5598373
    Abstract: A defect remedy LSI mounted on a memory module, comprising: an input interface portion for capturing address and control signals, the input interface portion being the same as that of a dynamic RAM; an input/output interface portion corresponding to a data bus of a memory device comprised of a plurality of dynamic random access memories; a memory circuit to which a chip address and an X defective address of any of the plurality of random access memories are electrically written, the memory circuit being substantially made nonvolatile; a redundancy remedy RAM portion composed of a static RAM wherein a word line is selected by a compare match signal between an X address signal and the defective address of the memory circuit, the X address signal and the defective address being captured via the input interface portion, and a column is selected by a Y address signal captured via the input interface portion; a selecting portion for connecting a data input/output bus of the redundancy remedy RAM portion to an input
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: January 28, 1997
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Shoji Wada, Kanehide Kenmizaki, Masaya Muranaka, Masahiro Ogata, Hidetomo Aoyagi, Tetsuya Kitame, Masahiro Katayama, Shoji Kubono, Yukihide Suzuki, Makoto Morino, Sinichi Miyatake, Seiichi Shundo, Yoshihisa Koyama, Nobuhiko Ohno
  • Patent number: 4907063
    Abstract: A semiconductor integrated circuit device is provided with polycrystalline silicon filling U-grooves etched in a semiconductor substrate to form isolation regions which prevent any short-circuiting between the polycrystalline silicon and electrodes or wiring formed on the semiconductor substrate. A silicon dioxide film is formed within the U-grooves, and a silicon nitride film and a silicon dioxide film are further formed thereon. The silicon nitride film has a high hardness which suppresses the development of crystal defects in the peripheral active regions due to the expansion of the surface of the polycrystalline silicon when it is oxidized. When the surface of the polycrystalline silicon is oxidized, the oxidation proceeds along the oxide film over the nitride film, so that the whole of the oxide film is formed thickly. Therefore, the silicon nitride film and the silicon dioxide film are provided with an increased margin against the etching used for forming contact holes.
    Type: Grant
    Filed: May 20, 1987
    Date of Patent: March 6, 1990
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering, Ltd.
    Inventors: Daisuke Okada, Akihisa Uchida, Toshihiko Takakura, Shinji Nakashima, Nobuhiko Ohno, Katsumi Ogiue
  • Patent number: 4700464
    Abstract: A semiconductor integrated circuit device is provided with polycrystalline silicon filling U-grooves etched in a semiconductor substrate to form isolation regions which prevent any short-circuiting between the polycrystalline silicon and electrodes or wiring formed on the semiconductor substrate. A silicon dioxide film is formed within the U-grooves, and a silicon nitride film and a silicon dioxide film are further formed thereon. The silicon nitride film has a high hardness which suppresses the development of crystal defects in the peripheral active regions due to the expansion of the surface of the polycrystalline silicon when it is oxidized. When the surface of the polycrystalline silicon is oxidized, the oxidation proceeds along the oxide film over the nitride film, so that the whole of the oxide film is formed thickly. Therefore, the silicon nitride film and the silicon dioxide film are provided with an increased margin against the etching used for forming contact holes.
    Type: Grant
    Filed: October 15, 1984
    Date of Patent: October 20, 1987
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering, Ltd.
    Inventors: Daisuke Okada, Akihisa Uchida, Toshihiko Takakura, Shinji Nakashima, Nobuhiko Ohno, Katsumi Ogiue
  • Patent number: 4656606
    Abstract: A read-only memory has a terminal for receiving a writing current and a data input/output terminal. In the writing operation, the writing current is supplied to the terminal which is different from the data input/output terminal. Therefore, a data output circuit can be constituted by an ECL circuit having a relatively low withstand voltage, and a selection circuit related to the reading operation is achieved by using an ECL circuit. Accordingly, the read-only memory performs the reading operation at high speeds. During the writing operation, a different selection circuit is used which can withstand high voltages.
    Type: Grant
    Filed: February 14, 1984
    Date of Patent: April 7, 1987
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Co Ltd
    Inventors: Nobuhiko Ohno, Katsumi Ogiue, Katsuya Mizue, Noriyoshi Okuda