Abstract: A digital signal is encoded for error correction, and the encoded digital signal is transmitted in M transmitting paths. The signal to be encoded occurs as N sequences of data words. A plurality n of sequences of error correcting words are generated from respective words of the N sequences delayed by respective different delay times of (D-di) words, where d.sub.i is a whole number associated with an ith one of the n error correcting word sequences. The resulting N data word sequences and n error correcting word sequences are provided with respective different total delay times, so that the total delays of the N sequences differ by an integral number D of words from one another. Blocks of the delayed N data sequences and n error correcting word sequences are formed and the blocks are cyclically distributed among the M transmitting paths. The values of M, N, n, D, and d.sub.i are selected so that the least common multiple of any two values of (d-d.sub.

Abstract: At least one channel of digitized information is recorded in at least one data track on a record medium by forming data blocks, each containing a predetermined number of data words representing the digitized information, and recording successive data blocks in at least one data track. A block address also is generated to identify each of the respective data blocks, this block address also being recorded with the data block in the data track. A predetermined number of successive data blocks is recorded in the data track in a sector interval. A control signal having at least a sector address for identifying the sector interval also is generated, and this control signal is recorded in a separate control track, successive control signals being recorded in successive sector intervals. The least significant bit of the sector address is coincident with the most significant bit of the block address, such that the block address is repeated with a periodicity related to the sector interval.

Abstract: Time base correcting apparatus is provided for a digital signal supplied to such apparatus in the form of successive data blocks with each data block including plural data words. A memory is provided, having plural addressable storage locations, each adapted to store a respective data block. A write address generator generates write-in addresses to address particular storage locations into which the supplied data blocks are written; and an error detector detects whether the supplied data block contains an error. If no error is detected, a write-in circuit writes that data block into the addressed storage location; but if an error is detected, the data block is inhibited from being stored. An error store also is provided to store an error flag which is, for example, reset when the nono-erroneous data block is written into the addressed storage location, and is set when an error in that data block is detected.

Abstract: At least one channel of digitized information is recorded in a selected number of data tracks by a record medium. The digitized information is encoded, modulated and then recorded in a predetermined number of tracks. For example, if n channels of digitized information are to be recorded in m data tracks, then each channel is recorded in m/n data tracks (m.gtoreq.n). A control signal is generated to include control data representing at least one of the following: (a) the number of data tracks in which each channel of digitized information is recorded, (b) the encoding scheme used to encode the information, (c) the type of modulation used to modulate the encoded information and (d) the relative speed of movement of the record medium. The control signal is recorded in a separate control track. Thus, the control signal represents the particular format in which the digitized information is recorded.

Abstract: A bit clock reproducing circuit produces an output bit clock signal in response to an input clock signal but without reproducing jitter present in the input signal. A counter is supplied with a reference clock signal as a counting input, and the counter is periodically loaded, at a fixed time during each cycle of the input clock signal, with data which is a predetermined function of the state of the counter at such times.

Abstract: An apparatus for recording and/or reproducing a serial digitized analog signal controls the transport speed of a recording medium according to the sampling rate employed in digitizing the analog signal to produce a constant data density on the recording medium regardless of the sampling rate selected. The frequency of a fundamental clock signal establishes the sampling frequency during recording. A coded timing signal also recorded on the recording medium includes both a sync signal and a coded identity of the sampling frequency in use. During reproduction, the coded identity of the sampling frequency is used to select the same fundamental clock signal as was used during recording and the reproduced sync signal is phase compared with a reference signal derived from the fundamental clock signal to correspondingly control the speed and phase of transport of the recording medium. The fundamental clock signal may be manually varied during reproduction for pitch control of the reproduced analog signal.

Abstract: A cooking apparatus comprises an apparatus housing divided by a partition plate into upper and lower chambers. An oven chamber is defined in the lower chamber and has a baking heater therein. A vessel having a kneading blade is disposed on the upper chamber. The upper chamber includes a drive mechanism for rotating the blade. A fermenting heater is provided below the bottom of the vessel to heat the interior of the vessel to a fermenting temperature. Dough is kneaded and fermented in the vessel and baked in the oven chamber. Another fermenting heater is disposed in the oven chamber to preheat the interior of the oven chamber for baking, while the dough is being kneaded and fermented in the vessel.