Abstract: As much tag information as corresponds to the number of blocks stored in main memories is stored in tag memories. The tag information indicates whether or not a processor belonging to a node other than the nodes containing tag memories has made an access request and the contents of a cache have been rewritten. Bus bridges perform cache coherency control, referring to the tag information. When the tag information indicates "Modified," the bus bridges stop the data read from the main memories and send the correct data to the requesting processor after a copy-back process of the modified block has been completed.

Abstract: In a cache memory control apparatus, a cache hit ratio of a cache memory is increased by employing both of control information (cacheable or non-cacheable) and condition information (invalidation or validation) to avoid unnecessary invalidation of the cache data. The microprocessor system with a cache memory control apparatus includes a microprocessor for processing various data. A main memory unit stores main data in a designated physical address allocated by a page unit. An auxiliary memory unit stores auxiliary data in a designated physical address allocated by a page unit. A cache memory temporarily stores a portion of the main data to be stored in the main memory unit. A virtual memory space manages by a virtual address to transfer the main data between the microprocessor and the main memory unit through the cache memory and also to transfer the auxiliary data between the microprocessor and the auxiliary memory units.

Abstract: In order to clip a figure using a predetermined frame, coordinate values of cross points defined by a line segment representing a figure to be clipped and each side of the clipping frame or each extension line thereof are detected. A positional relationship between the line segment and the clipping frame, and the presence/absence of the cross points on the clipping frame are obtained, respectively. By utilizing the above information, a new boundary line which does not exist in a figure before clipping can be extracted. Since the detection of cross point coordinates and the extraction of boundaries are independently processed, high-speed processing can be realized.

Abstract: A boundary detection target region designating circuit includes a maximum value register in which a predetermined minimum value is initially set, and a minimum value register in which a predetermined maximum value is initially set. The content of the maximum value register is compared with a vertex coordinate of a boundary written in a boundary detection memory by a first comparator. If it is detected that the vertex coordinate is larger than the content of the maximum value register, the content of the maximum value register is updated to be the vertex coordinate by a first updating means. The content of the minimum value register is compared with the vertex coordinate by a second comparator. If it is detected that the vertex coordinate is smaller than the content of the minimum value register, the content of the minimum value register is updated to be the vertex coordinate by a second updating means.

Abstract: In a graphic display apparatus having a digital differential analyzer (DDA), a chrominance data stored in a register is written in an area of a bit map memory defined by coordinates generated from DDA by a write control circuit in response to ARDY signal. A first flip-flop is reset by a busy signal from the write control circuit and is set by a load signal. When the first flip-flop is in a reset state, a first gate produces PRDY signal requesting a microprocessor to load the chrominance data in the register in response to RDY signal indicating completion of a coordinate setting operation from DDA. When the first flip-flop is in a set state, a second gate generates CRDY signal in response to RDY signal. CRDY and RDY signals are supplied to a selector which selects one of them due to a second flip-flop for switching a line processing mode and a raster operation mode, and supplies the selected signal to the write control circuit to thereby perform write operation.

Abstract: A color graphic display device for converting color index data read out from a plurality of frame memories to color information on a screen so as to perform graphic display has a first register for holding a group number determined in accordance with a combination of areas between copy source and destination memories of the plurality of frame memories for an interarea copy, and a ROM table for storing conversion color index data at a plurality of addresses of the group number and for receiving as address data linked data of an output from the first register and the color index data from the plurality of frame memories. The group number is set in the first register and the corresponding color index data is read out from the frame memories, thereby obtaining updated or converted color index data from the ROM table. The color graphic display device also has a second register for holding write enable/disable data for specifying the write enable/disable mode of the plurality of frame memories.

Abstract: A data prefetch apparatus provided between a main memory formed of a plurality of memory blocks and an I/O device whose data transfer speed is slower than that of the main memory, comprising an address counter for the main memory and a data buffer for storing the data prefetched from the main memory. In the data prefetch apparatus, a full/empty detector is connected to the data buffer and a memory block detector is connected to the address counter and the data prefetch is interrupted when the over-access of the one of the memory block is detected and is restarted when the data buffer is empty and data request is supplied from the I/O device.

Abstract: A graphic display device for shading the region between one straight line L.sub.1 connecting two points P.sub.1 and P.sub.2 and another straight line L.sub.2 parallel to the Y axis or the X axis, including a straight line coordinates generator to define a line L.sub.1 which connects the two points P.sub.1 and P.sub.2, an X or Y coordinates generator to count X or Y coordinates from a point T.sub.t on the line L.sub.1 given by the straight line coordinates generator in a predetermined direction, a controller for signalling the straight line coordinates generator when the X or Y coordinates generator completes generation of the coordinates for a selected shading line, a detector for detecting the intersections of the lines L.sub.1 and L.sub.2 in accordance with the number of the lattice points designated to provide shading on a selected shading line, a changer for changing the counting direction of the X or Y coordinates generator after detecting the intersection of the lines L.sub.1 and L.sub.

Abstract: A new and improved straight line coordinates generator to determine and generate the coordinates of a group of lattice points [P.sub.k (k=1, 2, . . . , n-1)] to simulate an actual line defined by connecting the two lattice points P.sub.O (X.sub.o, Y.sub.o) and P.sub.n (X.sub.n, Y.sub.n), on a secondary coordinates face comprises registers, adders, comparators, a clock generator gate circuit, X-coordinate counter for determining X-coordinate values, Y-coordinate counter for determining Y-coordinate values, an initializing device for setting the registers with initial normalizing values and a generator for sequentially generating each X and Y coordinate of the lattice points to simulate the line. The circuit arrangement of the straight line coordinates generator is simplified by eliminating the need for decimal points in determining the coordinates of the lattice points to be lightened or highlighted to form the simulated line.