Abstract: An end fixing structure of a composite wire rod includes a composite wire rod, a wedge body that is formed into a cylindrical shape with an enlarging diameter from a front end portion, wherein an inner wall surface is formed for engaging with the outer surface of the composite wire rod which is copied onto the inner wall surface, and a sleeve provided on an outer peripheral side of the wedge body and having a conical and hollow inner structure, and the wedge body consists of a plurality of divided wedge bodies, facing each other on their divided surfaces with a space therebetween, and the inner wall surface in the divided wedge body is made of microscopic irregularities, thereby shortening a processing time and maintaining a sufficient gripping power over long term.

Abstract: An end fixing structure of a composite wire rod includes a composite wire rod, a wedge body that is formed into a cylindrical shape with an enlarging diameter from a front end portion, wherein an inner wall surface is formed for engaging with the outer surface of the composite wire rod which is copied onto the inner wall surface, and a sleeve provided on an outer peripheral side of the wedge body and having a conical and hollow inner structure, and the wedge body consists of a plurality of divided wedge bodies, facing each other on their divided surfaces with a space therebetween, and the inner wall surface in the divided wedge body is made of microscopic irregularities, thereby shortening a processing time and maintaining a sufficient gripping power over long term.

Abstract: The present invention provides a sense amplifier including a current sense circuit that outputs a detection voltage corresponding to an electric current intended for comparison, a current sense circuit that outputs a reference voltage corresponding to an electric current for reference, and a comparison circuit that compares the detection voltage and the reference voltage and outputs the result of comparison thereby. In the sense amplifier, the current sense circuit is operated in accordance with a chip control signal, and the current sense circuit is operated by a delay chip control signal obtained by delaying the chip control signal by a predetermined time by means of a delay circuit. Thus, since the current sense circuit outputs a predetermined reference voltage when the operation of the current sense circuit is started, the detection voltage rapidly converges on a predetermined level without performing such a feedback operation as to repeat its abrupt rise and fall.

Abstract: The present invention provides a sense amplifier including a current sense circuit that outputs a detection voltage corresponding to an electric current intended for comparison, a current sense circuit that outputs a reference voltage corresponding to an electric current for reference, and a comparison circuit that compares the detection voltage and the reference voltage and outputs the result of comparison thereby. In the sense amplifier, the current sense circuit is operated in accordance with a chip control signal, and the current sense circuit is operated by a delay chip control signal obtained by delaying the chip control signal by a predetermined time by means of a delay circuit. Thus, since the current sense circuit outputs a predetermined reference voltage when the operation of the current sense circuit is started, the detection voltage rapidly converges on a predetermined level without performing such a feedback operation as to repeat its abrupt rise and fall.

Abstract: Read access to a memory device is controlled by comparing an input control code with a predetermined code stored in the memory device. The comparison is performed inside the memory device, and read access is enabled or disabled according to the result. The control code can be used to select one of several memory devices connected to a common bus, or to provide security for information stored in the memory device.

Abstract: Since the logic levels on both edge sides (node n1 and node n2) of an NMOS connected to a word line are set to the same level corresponding to the logic level of the chip enable signal, even in a memory having an MOS transistor with a short gate length due to an increase of the storage capacity, a leak voltage can be prevented from taking place in the chip standby state.