Patents by Inventor Nobuhiro Kaneko
Nobuhiro Kaneko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9146859Abstract: There is provided an information processing apparatus including a rewrite frequency management section configured to manage a rewrite frequency of a page included in a nonvolatile primary storage apparatus having an upper limit in the rewrite frequency, and a data processing section configured, when an instruction for writing write data to a predetermined page is issued and a rewrite frequency of the predetermined page reaches a threshold value that is less than the upper limit of the rewrite frequency of the primary storage apparatus, to write the write data to another page different from the predetermined page, the other page storing no effective data and having a rewrite frequency that does not reach the threshold value.Type: GrantFiled: May 15, 2013Date of Patent: September 29, 2015Assignee: SONY CORPORATIONInventors: Nobuhiro Kaneko, Hiroki Nagahama, Tetsuya Asayama, Tomohiro Katori, Katsuya Takahashi
-
Patent number: 8972659Abstract: There is provided a memory control device including a device driver that executes writing or reading of data to/from a main storage unit and temporary writing or reading of data to/from a cache unit including a plurality of cache blocks, and a control unit that issues an instruction for writing or reading of data of a file system to/from the main storage unit or the cache unit to the device driver. The control unit may notify priority information about a priority for data storage into a logical block to which the cache block is associated to the device driver.Type: GrantFiled: March 9, 2012Date of Patent: March 3, 2015Assignee: Sony CorporationInventors: Hiroaki Ishizawa, Nobuhiro Kaneko, Shusuke Saeki, Takashi Kida, Tomohiro Katori
-
Publication number: 20140181378Abstract: There is provided a control device including, a reading and writing control unit configured to control writing and reading of data on and from a non-volatile memory that has a plurality of blocks each set to be a unit for performing erasure of data. The non-volatile memory stores order information indicating an order of the blocks in which data is to be written. The reading and writing control unit selects a writing target block that is a target block for writing of data according to the order indicated by the order information, and writes data in the selected writing target block.Type: ApplicationFiled: December 13, 2013Publication date: June 26, 2014Applicant: SONY CORPORATIONInventors: Shusuke SAEKI, Kenji FUDONO, Nobuhiro KANEKO, Kazumi SATO
-
Publication number: 20130332661Abstract: There is provided an information processing apparatus including a rewrite frequency management section configured to manage a rewrite frequency of a page included in a nonvolatile primary storage apparatus having an upper limit in the rewrite frequency, and a data processing section configured, when an instruction for writing write data to a predetermined page is issued and a rewrite frequency of the predetermined page reaches a threshold value that is less than the upper limit of the rewrite frequency of the primary storage apparatus, to write the write data to another page different from the predetermined page, the other page storing no effective data and having a rewrite frequency that does not reach the threshold value.Type: ApplicationFiled: May 15, 2013Publication date: December 12, 2013Applicant: Sony CorporationInventors: Nobuhiro KANEKO, Hiroki Nagahama, Tetsuya Asayama, Tomohiro Katori, Katsuya Takahashi
-
Publication number: 20130332695Abstract: There is provided an information processing apparatus including a primary storage apparatus configured by combining a plurality of memories each having a different upper limit of a number of possible rewrites, and an allocation management section configured to allocate a storage area of data to be stored in the primary storage apparatus to one of the plurality of memories based on a rewrite frequency of the data.Type: ApplicationFiled: May 15, 2013Publication date: December 12, 2013Applicant: Sony CorporationInventors: Tomohiro KATORI, Tetsuya Asayama, Katsuya Takahashi, Hiroki Nagahama, Nobuhiro Kaneko
-
Publication number: 20130326123Abstract: There is provided a memory management device including a non-volatile memory that performs writing and reading of data on a per-page basis, and performs erasing on a per-block basis, and a control unit that manages a data process in the non-volatile memory by performing logical-physical translation on a per-translation unit (TU) basis, and performs a fold process. The control unit sets data of a physical TU corresponding to unnecessary logical TU information to be excluded from a copy target in the fold process based on the unnecessary logical TU information, the unnecessary logical TU information being notified of by a file system and representing a logical TU corresponding to a physical TU in which unnecessary data is physically written.Type: ApplicationFiled: May 23, 2013Publication date: December 5, 2013Applicant: Sony CorporationInventors: Shusuke SAEKI, Kenji FUDONO, Nobuhiro KANEKO, Kazumi SATO
-
Patent number: 8489850Abstract: A memory control method is disclosed which includes: a storing step of storing a logical to physical conversion table retaining relations of correspondence between addresses of logical blocks in a user data area on the one hand, and addresses of physical blocks assigned to the logical blocks on the other hand, along with addresses of physical blocks in a cache area, the physical block addresses corresponding to the physical block addresses in the logical to physical conversion table; a first writing step of writing, to a deleted new cache block in the cache area, data in excess of a designated logical boundary which defines a logical space size in units of a plurality of sectors within a user data block of the user data area; and a second writing step of writing the data starting from the beginning of the new cache block upon data write in the first writing step to the new cache block, regardless of the logical address space of the new cache block.Type: GrantFiled: November 30, 2006Date of Patent: July 16, 2013Assignee: Sony CorporationInventors: Nobuhiro Kaneko, Kenichi Nakanishi
-
Patent number: 8386713Abstract: Disclosed herein is a memory apparatus comprising: a nonvolatile memory configured to allow data to be written thereto and read therefrom in units of a cluster and to permit data to be deleted therefrom in units of a block made up of a plurality of sectors; a control circuit configured to control access operations to said nonvolatile memory; a management area; a user data area; and a cache area; said management area includes a logical/physical table, and the addresses of physical blocks in said cache area.Type: GrantFiled: September 9, 2008Date of Patent: February 26, 2013Assignee: Sony CorporationInventors: Nobuhiro Kaneko, Kenichi Nakanishi
-
Patent number: 8347056Abstract: A storage apparatus is disclosed which includes: a memory configured to have a plurality of pages to which data can be written in units of a page, the memory being further configured to have a plurality of pages of write data stored into each page in multi-valued form; and a control section configured to select pages to which to write the data from among the plurality of pages of the memory, the control section being further configured to write to the selected pages of the memory the data of at least two bits in multi-valued form for a plurality of pages including the selected pages; wherein, when writing the plurality of pages of the write data, the control section puts the write data into multi-valued form per page before writing the data to a plurality of different unused pages of the memory on a page-by-page basis.Type: GrantFiled: January 12, 2011Date of Patent: January 1, 2013Assignee: Sony CorporationInventors: Toshifumi Nishiura, Nobuhiro Kaneko, Hideaki Okubo
-
Publication number: 20120239884Abstract: There is provided a memory control device including a device driver that executes writing or reading of data to/from a main storage unit and temporary writing or reading of data to/from a cache unit including a plurality of cache blocks, and a control unit that issues an instruction for writing or reading of data of a file system to/from the main storage unit or the cache unit to the device driver. The control unit may notify priority information about a priority for data storage into a logical block to which the cache block is associated to the device driver.Type: ApplicationFiled: March 9, 2012Publication date: September 20, 2012Inventors: Hiroaki Ishizawa, Nobuhiro Kaneko, Shusuke Saeki, Takashi Kida, Tomohiro Katori
-
Publication number: 20120215964Abstract: There is provided a management device including a management unit that manages a nonvolatile memory configured to allow data to be written, read, or erased electrically, allow writing and reading to be performed in units of a page, and allow erasing to be performed in units of a block including a plurality of pages. The management unit divides a plurality of physical blocks of the nonvolatile memory into a virtual area including virtual blocks corresponding to the physical blocks, and an alternate area including alternate blocks for replacing defective physical blocks in the virtual area, manages the nonvolatile memory in management units of three stages including management of the physical blocks, management of the virtual blocks, and management of extended blocks, and writes to the nonvolatile memory first, second, and third management information for use in the management of the physical blocks, the virtual blocks, and the extended blocks, respectively.Type: ApplicationFiled: January 25, 2012Publication date: August 23, 2012Inventors: Nobuhiro KANEKO, Shusuke Saeki, Kenji Fudono, Kazunori Yamamoto
-
Publication number: 20120166713Abstract: An administration device includes an administration section. The administration section administers writing, reading, and erasing of data in a nonvolatile memory, in which the data can be electrically written, read, and erased and the writing and the reading are performed on a page-by-page basis and the erasing is performed on a block-by-block basis, by translating a logical address into a physical address on a per translation unit basis; and performs fold processing of increasing unwritten physical translation units by the number of written invalid physical translation units, which are contained in a block of a copy source, by copying data of written valid physical translation units among the contents of the block into a block, in which the unwritten physical translation units reside, and by erasing the block of the copy source.Type: ApplicationFiled: December 7, 2011Publication date: June 28, 2012Applicant: Sony CorporationInventors: Shusuke SAEKI, Kenji FUDONO, Nobuhiro KANEKO, Hiroki NAGAHAMA, Kazunori YAMAMOTO
-
Patent number: 8060684Abstract: Memory control apparatus, memory control method, and program are provided. The present invention provides a preparatory process for determining whether or not a data-updating process to update data of a flash memory or a data-writing process to write new data into the memory has been completed normally. A data-updating process to update data stored in a specific block is carried out as a process including alternate-block processing to replace the specific block with another block referred to as an alternate block. In the current data-updating process, the alternate block is examined to determine whether or not data has been erased from the alternate block. If data has been erased from the alternate block, the preceding data-updating or data-writing process is determined to be normal. By virtue of a property exhibited by the contents of the reserved-block address, the reserved-block address needs to be saved in the flash memory only once during a data-updating or data-writing process.Type: GrantFiled: September 6, 2005Date of Patent: November 15, 2011Assignee: Sony CorporationInventors: Kenichi Nakanishi, Nobuhiro Kaneko
-
Publication number: 20110179244Abstract: A storage apparatus is disclosed which includes: a memory configured to have a plurality of pages to which data can be written in units of a page, the memory being further configured to have a plurality of pages of write data stored into each page in multi-valued form; and a control section configured to select pages to which to write the data from among the plurality of pages of the memory, the control section being further configured to write to the selected pages of the memory the data of at least two bits in multi-valued form for a plurality of pages including the selected pages; wherein, when writing the plurality of pages of the write data, the control section puts the write data into multi-valued form per page before writing the data to a plurality of different unused pages of the memory on a page-by-page basis.Type: ApplicationFiled: January 12, 2011Publication date: July 21, 2011Applicant: SONY CORPORATIONInventors: Toshifumi Nishiura, Nobuhiro Kaneko, Hideaki Okubo
-
Patent number: 7647470Abstract: A memory device and controlling method for nonvolatile memory are provided. The memory device and the controlling method for a nonvolatile memory are provided by which, where a file management system wherein there is a tendency that lower logic addresses are used frequently like the MS-DOS is adopted, physical blocks of a flash memory are used in an averaged fashion and the life of the flash memory can be elongated thereby.Type: GrantFiled: August 19, 2005Date of Patent: January 12, 2010Assignee: Sony CorporationInventors: Junko Sasaki, Kenichi Nakanishi, Nobuhiro Kaneko
-
Publication number: 20090070517Abstract: Disclosed herein is a memory apparatus comprising: a nonvolatile memory configured to allow data to be written thereto and read therefrom in units of a cluster and to permit data to be deleted therefrom in units of a block made up of a plurality of sectors; a control circuit configured to control access operations to said nonvolatile memory; a management area; a user data area; and a cache area; said management area includes a logical/physical table, and the addresses of physical blocks in said cache area.Type: ApplicationFiled: September 9, 2008Publication date: March 12, 2009Applicant: SONY CORPORATIONInventors: Nobuhiro Kaneko, Kenichi Nakanishi
-
Patent number: 7444460Abstract: The invention provides a data storage device and a method of updating management information, capable of dealing with management information in a highly reliable manner so that information is not easily lost when an error occurs. File management information such as a FAT serving as address management information in a flash memory is stored in a management information area of the memory, a pair of blocks is assigned as blocks for use to store data of the FAT, and writing of updated FAT information is performed by alternately using the two blocks of the block pair such that previous FAT information is retained in one of the two blocks of the block pair, and updated FAT information is written in the other block of the block pair, whereby, even when an error occurs in the middle of the process of writing the updated management information, a process using the retained previous FAT information is possible.Type: GrantFiled: March 5, 2004Date of Patent: October 28, 2008Assignee: Sony CorporationInventors: Kenichi Nakanishi, Junko Sasaki, Nobuhiro Kaneko, Osamu Nagata, Hideaki Okubo
-
Publication number: 20070150693Abstract: A memory control method is disclosed which includes: a storing step of storing a logical to physical conversion table retaining relations of correspondence between addresses of logical blocks in a user data area on the one hand, and addresses of physical blocks assigned to the logical blocks on the other hand, along with addresses of physical blocks in a cache area, the physical block addresses corresponding to the physical block addresses in the logical to physical conversion table; a first writing step of writing, to a deleted new cache block in the cache area, data in excess of a designated logical boundary which defines a logical space size in units of a plurality of sectors within a user data block of the user data area; and a second writing step of writing the data starting from the beginning of the new cache block upon data write in the first writing step to the new cache block, regardless of the logical address space of the new cache block.Type: ApplicationFiled: November 30, 2006Publication date: June 28, 2007Applicant: SONY CORPORATIONInventors: Nobuhiro Kaneko, Kenichi Nakanishi
-
Publication number: 20060059297Abstract: Memory control apparatus, memory control method, and program are provided. The present invention provides a preparatory process for determining whether or not a data-updating process to update data of a flash memory or a data-writing process to write new data into the memory has been completed normally. A data-updating process to update data stored in a specific block is carried out as a process including alternate-block processing to replace the specific block with another block referred to as an alternate block. In the current data-updating process, the alternate block is examined to determine whether or not data has been erased from the alternate block. If data has been erased from the alternate block, the preceding data-updating or data-writing process is determined to be normal. By virtue of a property exhibited by the contents of the reserved-block address, the reserved-block address needs to be saved in the flash memory only once during a data-updating or data-writing process.Type: ApplicationFiled: September 6, 2005Publication date: March 16, 2006Inventors: Kenichi Nakanishi, Nobuhiro Kaneko
-
Publication number: 20060047889Abstract: A memory device and controlling method for nonvolatile memory are provided. The memory device and the controlling method for a nonvolatile memory are provided by which, where a file management system wherein there is a tendency that lower logic addresses are used frequently like the MS-DOS is adopted, physical blocks of a flash memory are used in an averaged fashion and the life of the flash memory can be elongated thereby.Type: ApplicationFiled: August 19, 2005Publication date: March 2, 2006Inventors: Junko Sasaki, Kenichi Nakanishi, Nobuhiro Kaneko