Patents by Inventor Nobuhiro Kasa

Nobuhiro Kasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7642618
    Abstract: Semiconductor devices are provided with high performance high-frequency circuits in which interference caused by inductors is reduced. In a semiconductor device including a modulator circuit to modulate a carrier wave by a base band signal to output an RF signal and a demodulator circuit to demodulate the RF signal by use of the carrier wave to gain the base band signal and a local oscillator to generate the carrier wave, inductors respectively having a closed loop wire are adopted. Interference caused by mutual inductance is reduced by the closed loop wire. For example, where inductors are adopted in the modulator circuit, a closed loop wire is disposed around the outer periphery of the inductors.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: January 5, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Nobuhiro Shiramizu, Takahiro Nakamura, Toru Masuda, Nobuhiro Kasa, Hiroshi Mori
  • Patent number: 7095999
    Abstract: A semiconductor integrated circuit comprising a first circuit block including an oscillation circuit considered to be a noise generator and a second circuit block including circuits considered to be easily affected by a noise generated by the oscillation circuit, being most likely led to a malfunction are created on a single semiconductor substrate with the first and second circuit blocks separated from each other. To put it more concretely, the first and second circuit blocks are respectively created in a first island area and a second island area on the surface of the semiconductor substrate. The first and second island areas are each enclosed by an insulating isolation band. A low-resistance semiconductor area is created in a base area excluding locations occupied by active elements in the first and second island areas and is connected to a stable voltage terminal.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: August 22, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Nobuhiro Kasa, Yoshiyasu Tashiro, Kazuaki Hori
  • Publication number: 20060038621
    Abstract: Semiconductor devices provided with high performance high-frequency circuits that reduce interference caused by inductors are provided. In the semiconductor device including a modulator circuit to modulate a carrier wave by a base band signal to output an RF signal and a demodulator circuit to demodulate the RF signal by use of the carrier wave to gain the base band signal and a local oscillator to generate the carrier wave, inductors respectively having a closed loop wire are adopted. Interference caused by mutual inductance is reduced by the closed loop wire. For example, where inductors are adopted in the modulator circuit, a closed loop wire is disposed around the outer periphery of the inductors.
    Type: Application
    Filed: July 19, 2005
    Publication date: February 23, 2006
    Inventors: Nobuhiro Shiramizu, Takahiro Nakamura, Toru Masuda, Nobuhiro Kasa, Hiroshi Mori
  • Patent number: 6621108
    Abstract: Disclosed herein is a semiconductor device wherein a thyristor protective element and a trigger element are provided in a semiconductor layer formed on a buried insulating layer, and a trigger electrode (gate) of the thyristor protective element and a back gate of the trigger element are provided in the same p well and electrically connected to each other to thereby drive the thyristor protective element based on a substrate current produced by the breakdown of the trigger element.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: September 16, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yoshiyasu Tashiro, Nobuhiro Kasa, Kousuke Okuyama, Hiroyasu Ishizuka
  • Publication number: 20030060183
    Abstract: A semiconductor integrated circuit comprising a first circuit block including an oscillation circuit considered to be a noise generator and a second circuit block including circuits considered to be easily affected by a noise generated by the oscillation circuit, being most likely led to a malfunction are created on a single semiconductor substrate with the first and second circuit blocks separated from each other. To put it more concretely, the first and second circuit blocks are respectively created in a first island area and a second island area on the surface of the semiconductor substrate. The first and second island areas are each enclosed by an insulating isolation band. A low-resistance semiconductor area is created in a base area excluding locations occupied by active elements in the first and second island areas and is connected to a stable voltage terminal.
    Type: Application
    Filed: November 7, 2002
    Publication date: March 27, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Nobuhiro Kasa, Yoshiyasu Tashiro, Kazuaki Hori
  • Patent number: 6501330
    Abstract: A semiconductor integrated circuit comprising a first circuit block including an oscillation circuit considered to be a noise generator and a second circuit block including circuits considered to be easily affected by a noise generated by the oscillation circuit, being most likely led to a malfunction are created on a single semiconductor substrate with the first and second circuit blocks separated from each other. To put it more concretely, the first and second circuit blocks are respectively created in a first island area and a second island area on the surface of the semiconductor substrate. The first and second island areas are each enclosed by an insulating isolation band. A low-resistance semiconductor area is created in a base area excluding locations occupied by active elements in the first and second island areas and is connected to a stable voltage terminal.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: December 31, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Nobuhiro Kasa, Yoshiyasu Tashiro, Kazuaki Hori
  • Publication number: 20020079958
    Abstract: A semiconductor integrated circuit comprising a first circuit block including an oscillation circuit considered to be a noise generator and a second circuit block including circuits considered to be easily affected by a noise generated by the oscillation circuit, being most likely led to a malfunction are created on a single semiconductor substrate with the first and second circuit blocks separated from each other. To put it more concretely, the first and second circuit blocks are respectively created in a first island area and a second island area on the surface of the semiconductor substrate. The first and second island areas are each enclosed by an insulating isolation band. A low-resistance semiconductor area is created in a base area excluding locations occupied by active elements in the first and second island areas and is connected to a stable voltage terminal.
    Type: Application
    Filed: March 5, 2002
    Publication date: June 27, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Nobuhiro Kasa, Yoshiyasu Tashiro, Kazuaki Hori
  • Patent number: 6384676
    Abstract: A semiconductor integrated circuit comprising a first circuit block including an oscillation circuit considered to be a noise generator and a second circuit block including circuits considered to be easily affected by a noise generated by the oscillation circuit, being most likely led to a malfunction are created on a single semiconductor substrate with the first and second circuit blocks separated from each other. To put it more concretely, the first and second circuit blocks are respectively created in a first island area and a second island area on the surface of the semiconductor substrate. The first and second island areas are each enclosed by an insulating isolation band. A low-resistance semiconductor area is created in a base area excluding locations occupied by active elements in the first and second island areas and is connected to a stable voltage terminal.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: May 7, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Nobuhiro Kasa, Yoshiyasu Tashiro, Kazuaki Hori
  • Publication number: 20010025963
    Abstract: Disclosed herein is a semiconductor device wherein a thyristor protective element and a trigger element are provided in a semiconductor layer formed on a buried insulating layer, and a trigger electrode (gate) of the thyristor protective element and a back gate of the trigger element are provided in the same p well and electrically connected to each other to thereby drive the thyristor protective element based on a substrate current produced by the breakdown of the trigger element.
    Type: Application
    Filed: March 13, 2001
    Publication date: October 4, 2001
    Inventors: Yoshiyasu Tashiro, Nobuhiro Kasa, Kousuke Okuyama, Hiroyasu Ishizuka
  • Publication number: 20010017568
    Abstract: A semiconductor integrated circuit comprising a first circuit block including an oscillation circuit considered to be a noise generator and a second circuit block including circuits considered to be easily affected by a noise generated by the oscillation circuit, being most likely led to a malfunction are created on a single semiconductor substrate with the first and second circuit blocks separated from each other. To put it more concretely, the first and second circuit blocks are respectively created in a first island area and a second island area on the surface of the semiconductor substrate. The first and second island areas are each enclosed by an insulating isolation band. A low-resistance semiconductor area is created in a base area excluding locations occupied by active elements in the first and second island areas and is connected to a stable voltage terminal.
    Type: Application
    Filed: February 22, 2001
    Publication date: August 30, 2001
    Inventors: Nobuhiro Kasa, Yoshiyasu Tashiro, Kazuaki Hori