Patents by Inventor Nobuhiro Konishi
Nobuhiro Konishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8187966Abstract: A Cu-CMP step applied to processes for 130 nm, 90 nm, and 65 nm technical nodes or the like mainly employs slurry to which an anticorrosive agent is added for preventing corrosion of Cu wiring. The inventors of the present application have studied and clearly found that in the Cu-CMP step using the slurry with the anticorrosive agent added thereto, the anticorrosive agent often forms complexes with Cu, which remain as foreign matter on a wafer in large quantity, leading to a reduction in yield, and in reliability of TDDB characteristics of the Cu wiring. In the invention of the present application, a post-CMP cleaning process involves applying wet cleaning to a wafer by supplying a cleaning solution, such as a chemical solution or pure water, to a device surface of the wafer substantially in a vertical direction with respect to the horizontal device surface, while rotating the wafer substantially about its center in the horizontal plane.Type: GrantFiled: March 25, 2009Date of Patent: May 29, 2012Assignee: Renesas Electronics CorporationInventors: Hiroyuki Masuda, Hiroshi Oshita, Nobuhiro Konishi
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Publication number: 20090286392Abstract: A Cu-CMP step applied to processes for 130 nm, 90 nm, and 65 nm technical nodes or the like mainly employs slurry to which an anticorrosive agent is added for preventing corrosion of Cu wiring. The inventors of the present application have studied and clearly found that in the Cu-CMP step using the slurry with the anticorrosive agent added thereto, the anticorrosive agent often forms complexes with Cu, which remain as foreign matter on a wafer in large quantity, leading to a reduction in yield, and in reliability of TDDB characteristics of the Cu wiring. In the invention of the present application, a post-CMP cleaning process involves applying wet cleaning to a wafer by supplying a cleaning solution, such as a chemical solution or pure water, to a device surface of the wafer substantially in a vertical direction with respect to the horizontal device surface, while rotating the wafer substantially about its center in the horizontal plane.Type: ApplicationFiled: March 25, 2009Publication date: November 19, 2009Inventors: Hiroyuki Masuda, Hiroshi Oshita, Nobuhiro Konishi
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Patent number: 7172963Abstract: In the forming process of buried wirings by filling wiring trenches formed in an insulator with a conductive film mainly made of Cu, the buried wirings are formed to have a uniform-height regardless of the width and density of the wiring trenches. When polishing a barrier conductor film comprised of a Ta film in the CMP process for forming the buried wirings, the polishing agent, which controls the removal rate of the underlying insulator of a silicon oxide film relative to the barrier conductor film to almost one twentieth or less, is used as the slurry, and the pad which is made of polyurethane with a hardness of 75 degrees or more measured by the Type E durometer in conformity with the JIS K6253 and which is comprised of the foam including non-uniform pores with a diameter of about 150 ?m or larger and a density of about 0.4–0.16 g/cm3, is used as the polishing pad.Type: GrantFiled: June 9, 2004Date of Patent: February 6, 2007Assignee: Renesas Technology Corp.Inventors: Yohei Yamada, Nobuhiro Konishi
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Patent number: 7084063Abstract: The copper interconnect formed by the use of a damascene technique is improved in dielectric breakdown strength (reliability). During post-CMP cleaning, alkali cleaning, a deoxidizing process due to hydrogen annealing or the like, and acid cleaning are carried out in this order. After the post-CMP cleaning and before forming an insulation film for a cap film, hydrogen plasma and ammonia plasma processes are carried out on the semiconductor substrate. In this way, a copper-based buried interconnect is formed in an interlayer insulation film structured of an insulation material having a low dielectric constant.Type: GrantFiled: December 23, 2003Date of Patent: August 1, 2006Assignee: Hitachi, Ltd.Inventors: Junji Noguchi, Shoji Asaka, Nobuhiro Konishi, Naohumi Ohashi, Hiroyuki Maruyama
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Patent number: 6949478Abstract: A method of forming an oxide film having high insularity capability is performed within an ultra clean environment, using charged particles.Type: GrantFiled: April 11, 2002Date of Patent: September 27, 2005Inventors: Tadahiro Ohmi, Takashi Imaoka, Hisayuki Shimada, Nobuhiro Konishi, Mizuho Morita, Takeo Yamashita, Tadashi Shibata, Hidetoshi Wakamatsu, Jinzo Watanabe, Shintaro Aoyama, Masakazu Nakamura
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Publication number: 20050206018Abstract: Vacuum processing equipment capable of preventing particles from sticking to objects to be processed in vacuum vessels. The vacuum equipment comprises a series of vacuum vessels separated by doors, and the pressure in the vessels are reducible respectively. The vessels are so configured that objects to be processed are moveable among them and there is provided light projection means for projecting ultra rays on gases introduced to at least of the vessels.Type: ApplicationFiled: May 13, 2005Publication date: September 22, 2005Inventors: Tadahiro Ohmi, Takashi Imaoka, Hisayuki Shimada, Nobuhiro Konishi, Mizuho Morita, Takeo Yamashita, Tadashi Shibata, Hidetoshi Wakamatsu, Jinzo Watanabe, Shintaro Aoyama, Masakazu Nakamura
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Publication number: 20050003670Abstract: In the forming process of buried wirings by filling wiring trenches formed in an insulator with a conductive film mainly made of Cu, the buried wirings are formed to have a uniform-height regardless of the width and density of the wiring trenches. When polishing a barrier conductor film comprised of a Ta film in the CMP process for forming the buried wirings, the polishing agent which can control the removal rate of the underlying insulator of a silicon oxide film relative to the barrier conductor film to almost one twentieth or less is used as the slurry, and the pad made of polyurethane with a hardness of 75 degrees or more measured by the Type E durometer in conformity with the JIS K6253, which is comprised of the foam including non-uniform pores with a diameter of about 150 ?m or larger and a density of about 0.4-0.6 g/cm3, is used as the polishing pad.Type: ApplicationFiled: June 9, 2004Publication date: January 6, 2005Inventors: Yohei Yamada, Nobuhiro Konishi
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Publication number: 20040147127Abstract: The copper interconnect formed by the use of a damascene technique is improved in dielectric breakdown strength (reliability). During post-CMP cleaning, alkali cleaning, a deoxidizing process due to hydrogen annealing or the like, and acid cleaning are carried out in this order. After the post-CMP cleaning and before forming an insulation film for a cap film, hydrogen plasma and ammonia plasma processes are carried out on the semiconductor substrate. In this way, a copper-based buried interconnect is formed in an interlayer insulation film structured of an insulation material having a low dielectric constant.Type: ApplicationFiled: December 23, 2003Publication date: July 29, 2004Inventors: Junji Noguchi, Shoji Asaka, Nobuhiro Konishi, Naohumi Ohashi, Hiroyuki Maruyama
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Patent number: 6723631Abstract: The copper interconnect formed by the use of a damascene technique is improved in dielectric breakdown strength (reliability). During post-CMP cleaning, alkali cleaning, a deoxidizing process due to hydrogen annealing or the like, and acid cleaning are carried out in this order. After the post-CMP cleaning and before forming an insulation film for a cap film, hydrogen plasma and ammonia plasma processes are carried out on the semiconductor substrate. In this way, a copper-based buried interconnect is formed in an interlayer insulation film structured of an insulation material having a low dielectric constant.Type: GrantFiled: September 28, 2001Date of Patent: April 20, 2004Assignee: Renesas Technology CorporationInventors: Junji Noguchi, Shoji Asaka, Nobuhiro Konishi, Naohumi Ohashi, Hiroyuki Maruyama
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Publication number: 20030073278Abstract: Vacuum processing equipment capable of preventing particles from sticking to objects to be processed in vacuum vessels. The vacuum equipment comprises a series of vacuum vessels separated by doors, and the pressure in the vessels are reducible respectively. The vessels are so configured that objects to be processed are movable among them, and there is provided light projection means for projecting ultra rays on gases introduced to at least of the vessels.Type: ApplicationFiled: April 11, 2002Publication date: April 17, 2003Inventors: Tadahiro Ohmi, Takashi Imaoka, Hisayuki Shimada, Nobuhiro Konishi, Mizuho Morita, Takeo Yamashita, Tadashi Shibata, Hidetoshi Wakamatsu, Jinzo Watanabe, Shintaro Aoyama, Masakazu Nakamura
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Publication number: 20020042193Abstract: The copper interconnect formed by the use of a damascene technique is improved in dielectric breakdown strength (reliability). During post-CMP cleaning, alkali cleaning, deoxidizing process due to hydrogen anneal or the like and acid cleaning are carried out in the order. After the post-CMP cleaning and before forming an insulation film for a cap film, hydrogen plasma and ammonia plasma processes are carried out on the semiconductor substrate. In this manner, a copper-based buried interconnect is formed in an interlayer insulation film structured of an insulation material having a low dielectric constant.Type: ApplicationFiled: September 28, 2001Publication date: April 11, 2002Inventors: Junji Noguchi, Shoji Asaka, Nobuhiro Konishi, Naohumi Ohashi, Hiroyuki Maruyama
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Patent number: 6147001Abstract: A method of manufacturing a semiconductor integrated circuit wherein a patterned wafer polishing machine for uniformly polishing a surface by chemical mechanical polishing is utilized which is provided with a head for holding a wafer and rubbing it on an abrasive surface. A pressure plate provided with vents is held by the head body which is provided with a gas inlet and an elastic film for sealing vents is provided on the end face on the side reverse to the gas inlet side of the pressure plate. A patterned wafer is held by the head as the wafer, pressed by action of the pressure of air from the gas inlet via the elastic film is pressed mechanically by the pressure plate. The polishing surface which is a principal plane on the patterned side of the wafer is mechanochemically polished by the abrasive surface.Type: GrantFiled: April 24, 1997Date of Patent: November 14, 2000Assignee: Hitachi, Ltd.Inventors: Takeshi Kimura, Hidefumi Ito, Hiroyuki Kojima, Nobuhiro Konishi, Yuuichirou Taguma, Shinichiro Mitani
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Patent number: 6146135Abstract: Vacuum processing equipment capable of preventing particles from sticking to objects to be processed in vacuum vessels. The vacuum equipment comprises a series of vacuum vessels separated by doors, and the pressure in the vessels are reducible respectively. The vessels are so configured that objects to be processed are movable among them, and there is provided light projection means for projecting ultra rays on gases introduced to at least of the vessels.Type: GrantFiled: July 9, 1996Date of Patent: November 14, 2000Assignees: Tadahiro Ohmi, Takasago Netsugaku Kogyo Kabushiki KaishaInventors: Jinzo Watanabe, Takeo Yamashita, Masakazu Nakamura, Shintaro Aoyama, Hidetoshi Wakamatsu, Tadashi Shibata, Tadahiro Ohmi, Nobuhiro Konishi, Mizuho Morita, Hisayuki Shimada, Takashi Imaoka